OpenWrt – Blame information for rev 2

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1 office 1 From 6eeff55fd4756f271ad09a914078c9aa45f8359d Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Fri, 16 Nov 2018 14:23:40 +0800
4 Subject: [PATCH 04/39] arch: support layerscape
5 This is an integrated patch of arch for layerscape
6  
7 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 Signed-off-by: Alison Wang <alison.wang@freescale.com>
9 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
10 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
11 Signed-off-by: Dave Liu <daveliu@freescale.com>
12 Signed-off-by: Guanhua <guanhua.gao@nxp.com>
13 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
14 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
15 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
16 Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
17 Signed-off-by: Jin Qing <b24347@freescale.com>
18 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
19 Signed-off-by: Li Yang <leoli@freescale.com>
20 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
21 Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
22 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
23 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
24 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
25 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
26 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
27 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
28 Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
29 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
30 Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
31 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
32 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
33 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
34 Signed-off-by: Biwen Li <biwen.li@nxp.com>
35 ---
36 arch/arm/include/asm/delay.h | 16 ++++++++++++++
37 arch/arm/include/asm/io.h | 31 +++++++++++++++++++++++++++
38 arch/arm/include/asm/mach/map.h | 4 ++--
39 arch/arm/include/asm/pgtable.h | 7 ++++++
40 arch/arm/kernel/time.c | 3 +++
41 arch/arm/mm/dma-mapping.c | 1 +
42 arch/arm/mm/ioremap.c | 7 ++++++
43 arch/arm/mm/mmu.c | 9 ++++++++
44 arch/arm64/include/asm/cache.h | 2 +-
45 arch/arm64/include/asm/io.h | 1 +
46 arch/arm64/include/asm/pgtable-prot.h | 3 +++
47 arch/arm64/include/asm/pgtable.h | 5 +++++
48 arch/arm64/mm/dma-mapping.c | 1 +
49 arch/arm64/mm/init.c | 12 +++++++----
50 14 files changed, 95 insertions(+), 7 deletions(-)
51  
52 --- a/arch/arm/include/asm/delay.h
53 +++ b/arch/arm/include/asm/delay.h
54 @@ -85,6 +85,22 @@ extern void __bad_udelay(void);
55 __const_udelay((n) * UDELAY_MULT)) : \
56 __udelay(n))
57  
58 +#define spin_event_timeout(condition, timeout, delay) \
59 +({ \
60 + typeof(condition) __ret; \
61 + int i = 0; \
62 + while (!(__ret = (condition)) && (i++ < timeout)) { \
63 + if (delay) \
64 + udelay(delay); \
65 + else \
66 + cpu_relax(); \
67 + udelay(1); \
68 + } \
69 + if (!__ret) \
70 + __ret = (condition); \
71 + __ret; \
72 +})
73 +
74 /* Loop-based definitions for assembly code. */
75 extern void __loop_delay(unsigned long loops);
76 extern void __loop_udelay(unsigned long usecs);
77 --- a/arch/arm/include/asm/io.h
78 +++ b/arch/arm/include/asm/io.h
79 @@ -128,6 +128,7 @@ static inline u32 __raw_readl(const vola
80 #define MT_DEVICE_NONSHARED 1
81 #define MT_DEVICE_CACHED 2
82 #define MT_DEVICE_WC 3
83 +#define MT_MEMORY_RW_NS 4
84 /*
85 * types 4 onwards can be found in asm/mach/map.h and are undefined
86 * for ioremap
87 @@ -229,6 +230,34 @@ void __iomem *pci_remap_cfgspace(resourc
88 #endif
89 #endif
90  
91 +/* access ports */
92 +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
93 +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
94 +
95 +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
96 +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
97 +
98 +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
99 +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
100 +
101 +/* Clear and set bits in one shot. These macros can be used to clear and
102 + * set multiple bits in a register using a single read-modify-write. These
103 + * macros can also be used to set a multiple-bit bit pattern using a mask,
104 + * by specifying the mask in the 'clear' parameter and the new bit pattern
105 + * in the 'set' parameter.
106 + */
107 +
108 +#define clrsetbits_be32(addr, clear, set) \
109 + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
110 +#define clrsetbits_le32(addr, clear, set) \
111 + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
112 +#define clrsetbits_be16(addr, clear, set) \
113 + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
114 +#define clrsetbits_le16(addr, clear, set) \
115 + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
116 +#define clrsetbits_8(addr, clear, set) \
117 + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
118 +
119 /*
120 * IO port access primitives
121 * -------------------------
122 @@ -417,6 +446,8 @@ void __iomem *ioremap_wc(resource_size_t
123 #define ioremap_wc ioremap_wc
124 #define ioremap_wt ioremap_wc
125  
126 +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
127 +
128 void iounmap(volatile void __iomem *iomem_cookie);
129 #define iounmap iounmap
130  
131 --- a/arch/arm/include/asm/mach/map.h
132 +++ b/arch/arm/include/asm/mach/map.h
133 @@ -21,9 +21,9 @@ struct map_desc {
134 unsigned int type;
135 };
136  
137 -/* types 0-3 are defined in asm/io.h */
138 +/* types 0-4 are defined in asm/io.h */
139 enum {
140 - MT_UNCACHED = 4,
141 + MT_UNCACHED = 5,
142 MT_CACHECLEAN,
143 MT_MINICLEAN,
144 MT_LOW_VECTORS,
145 --- a/arch/arm/include/asm/pgtable.h
146 +++ b/arch/arm/include/asm/pgtable.h
147 @@ -119,6 +119,13 @@ extern pgprot_t pgprot_s2_device;
148 #define pgprot_noncached(prot) \
149 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
150  
151 +#define pgprot_cached(prot) \
152 + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
153 +
154 +#define pgprot_cached_ns(prot) \
155 + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
156 + L_PTE_MT_DEV_NONSHARED)
157 +
158 #define pgprot_writecombine(prot) \
159 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
160  
161 --- a/arch/arm/kernel/time.c
162 +++ b/arch/arm/kernel/time.c
163 @@ -12,6 +12,7 @@
164 * reading the RTC at bootup, etc...
165 */
166 #include <linux/clk-provider.h>
167 +#include <linux/clockchips.h>
168 #include <linux/clocksource.h>
169 #include <linux/errno.h>
170 #include <linux/export.h>
171 @@ -121,5 +122,7 @@ void __init time_init(void)
172 of_clk_init(NULL);
173 #endif
174 timer_probe();
175 +
176 + tick_setup_hrtimer_broadcast();
177 }
178 }
179 --- a/arch/arm/mm/dma-mapping.c
180 +++ b/arch/arm/mm/dma-mapping.c
181 @@ -2416,6 +2416,7 @@ void arch_setup_dma_ops(struct device *d
182 #endif
183 dev->archdata.dma_ops_setup = true;
184 }
185 +EXPORT_SYMBOL(arch_setup_dma_ops);
186  
187 void arch_teardown_dma_ops(struct device *dev)
188 {
189 --- a/arch/arm/mm/ioremap.c
190 +++ b/arch/arm/mm/ioremap.c
191 @@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t
192 }
193 EXPORT_SYMBOL(ioremap_wc);
194  
195 +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
196 +{
197 + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
198 + __builtin_return_address(0));
199 +}
200 +EXPORT_SYMBOL(ioremap_cache_ns);
201 +
202 /*
203 * Remap an arbitrary physical address space into the kernel virtual
204 * address space as memory. Needed when the kernel wants to execute
205 --- a/arch/arm/mm/mmu.c
206 +++ b/arch/arm/mm/mmu.c
207 @@ -315,6 +315,13 @@ static struct mem_type mem_types[] __ro_
208 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
209 .domain = DOMAIN_KERNEL,
210 },
211 + [MT_MEMORY_RW_NS] = {
212 + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
213 + L_PTE_XN,
214 + .prot_l1 = PMD_TYPE_TABLE,
215 + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
216 + .domain = DOMAIN_KERNEL,
217 + },
218 [MT_ROM] = {
219 .prot_sect = PMD_TYPE_SECT,
220 .domain = DOMAIN_KERNEL,
221 @@ -651,6 +658,7 @@ static void __init build_mem_type_table(
222 }
223 kern_pgprot |= PTE_EXT_AF;
224 vecs_pgprot |= PTE_EXT_AF;
225 + mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
226  
227 /*
228 * Set PXN for user mappings
229 @@ -679,6 +687,7 @@ static void __init build_mem_type_table(
230 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
231 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
232 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
233 + mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
234 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
235 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
236 mem_types[MT_ROM].prot_sect |= cp->pmd;
237 --- a/arch/arm64/include/asm/cache.h
238 +++ b/arch/arm64/include/asm/cache.h
239 @@ -34,7 +34,7 @@
240 #define ICACHE_POLICY_VIPT 2
241 #define ICACHE_POLICY_PIPT 3
242  
243 -#define L1_CACHE_SHIFT 7
244 +#define L1_CACHE_SHIFT 6
245 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
246  
247 /*
248 --- a/arch/arm64/include/asm/io.h
249 +++ b/arch/arm64/include/asm/io.h
250 @@ -186,6 +186,7 @@ extern void __iomem *ioremap_cache(phys_
251 #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
252 #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
253 #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
254 +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
255 #define iounmap __iounmap
256  
257 /*
258 --- a/arch/arm64/include/asm/pgtable-prot.h
259 +++ b/arch/arm64/include/asm/pgtable-prot.h
260 @@ -48,6 +48,8 @@
261 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
262 #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
263 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
264 +#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
265 +
266  
267 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
268 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
269 @@ -68,6 +70,7 @@
270 #define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
271  
272 #define PAGE_S2 __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
273 +#define PAGE_S2_NS __pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
274 #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
275  
276 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
277 --- a/arch/arm64/include/asm/pgtable.h
278 +++ b/arch/arm64/include/asm/pgtable.h
279 @@ -377,6 +377,11 @@ static inline int pmd_protnone(pmd_t pmd
280 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
281 #define pgprot_writecombine(prot) \
282 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
283 +#define pgprot_cached(prot) \
284 + __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
285 + PTE_PXN | PTE_UXN)
286 +#define pgprot_cached_ns(prot) \
287 + __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
288 #define pgprot_device(prot) \
289 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
290 #define __HAVE_PHYS_MEM_ACCESS_PROT
291 --- a/arch/arm64/mm/dma-mapping.c
292 +++ b/arch/arm64/mm/dma-mapping.c
293 @@ -937,3 +937,4 @@ void arch_setup_dma_ops(struct device *d
294 }
295 #endif
296 }
297 +EXPORT_SYMBOL(arch_setup_dma_ops);
298 --- a/arch/arm64/mm/init.c
299 +++ b/arch/arm64/mm/init.c
300 @@ -457,6 +457,14 @@ void __init arm64_memblock_init(void)
301 * Register the kernel text, kernel data, initrd, and initial
302 * pagetables with memblock.
303 */
304 +
305 + /* make this the first reservation so that there are no chances of
306 + * overlap
307 + */
308 + reserve_elfcorehdr();
309 +
310 + reserve_crashkernel();
311 +
312 memblock_reserve(__pa_symbol(_text), _end - _text);
313 #ifdef CONFIG_BLK_DEV_INITRD
314 if (initrd_start) {
315 @@ -476,10 +484,6 @@ void __init arm64_memblock_init(void)
316 else
317 arm64_dma_phys_limit = PHYS_MASK + 1;
318  
319 - reserve_crashkernel();
320 -
321 - reserve_elfcorehdr();
322 -
323 high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
324  
325 dma_contiguous_reserve(arm64_dma_phys_limit);