OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | #include "vr9.dtsi" |
2 | |||
3 | #include <dt-bindings/input/input.h> |
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4 | #include <dt-bindings/mips/lantiq_rcu_gphy.h> |
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5 | |||
6 | / { |
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7 | memory@0 { |
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8 | reg = <0x0 0x7f00000>; |
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9 | }; |
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10 | |||
11 | usb_vbus: regulator-usb-vbus { |
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12 | compatible = "regulator-fixed"; |
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13 | |||
14 | regulator-name = "USB_VBUS"; |
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15 | |||
16 | regulator-min-microvolt = <5000000>; |
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17 | regulator-max-microvolt = <5000000>; |
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18 | |||
19 | gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; |
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20 | enable-active-high; |
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21 | }; |
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22 | }; |
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23 | |||
24 | ð0 { |
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25 | lan: interface@0 { |
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26 | compatible = "lantiq,xrx200-pdi"; |
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27 | #address-cells = <1>; |
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28 | #size-cells = <0>; |
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29 | reg = <0>; |
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30 | mtd-mac-address = <&romfile 0xf100>; |
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31 | lantiq,switch; |
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32 | |||
33 | ethernet@0 { |
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34 | compatible = "lantiq,xrx200-pdi-port"; |
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35 | reg = <0>; |
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36 | phy-mode = "rgmii"; |
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37 | phy-handle = <&phy0>; |
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38 | // gpios = <&gpio 42 GPIO_ACTIVE_LOW>; |
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39 | }; |
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40 | ethernet@5 { |
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41 | compatible = "lantiq,xrx200-pdi-port"; |
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42 | reg = <5>; |
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43 | phy-mode = "rgmii"; |
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44 | phy-handle = <&phy5>; |
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45 | }; |
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46 | ethernet@2 { |
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47 | compatible = "lantiq,xrx200-pdi-port"; |
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48 | reg = <2>; |
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49 | phy-mode = "gmii"; |
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50 | phy-handle = <&phy11>; |
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51 | }; |
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52 | ethernet@3 { |
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53 | compatible = "lantiq,xrx200-pdi-port"; |
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54 | reg = <4>; |
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55 | phy-mode = "gmii"; |
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56 | phy-handle = <&phy13>; |
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57 | }; |
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58 | }; |
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59 | |||
60 | mdio@0 { |
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61 | #address-cells = <1>; |
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62 | #size-cells = <0>; |
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63 | compatible = "lantiq,xrx200-mdio"; |
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64 | reg = <0>; |
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65 | |||
66 | phy0: ethernet-phy@0 { |
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67 | reg = <0x0>; |
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68 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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69 | }; |
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70 | phy5: ethernet-phy@5 { |
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71 | reg = <0x5>; |
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72 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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73 | }; |
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74 | phy11: ethernet-phy@11 { |
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75 | reg = <0x11>; |
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76 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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77 | }; |
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78 | phy13: ethernet-phy@13 { |
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79 | reg = <0x13>; |
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80 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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81 | }; |
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82 | }; |
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83 | }; |
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84 | |||
85 | &gphy0 { |
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86 | lantiq,gphy-mode = <GPHY_MODE_GE>; |
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87 | }; |
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88 | |||
89 | &gphy1 { |
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90 | lantiq,gphy-mode = <GPHY_MODE_GE>; |
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91 | }; |
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92 | |||
93 | &gpio { |
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94 | pinctrl-names = "default"; |
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95 | pinctrl-0 = <&state_default>; |
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96 | |||
97 | state_default: pinmux { |
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98 | mdio { |
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99 | lantiq,groups = "mdio"; |
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100 | lantiq,function = "mdio"; |
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101 | }; |
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102 | gphy-leds { |
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103 | lantiq,groups = "gphy0 led1", "gphy1 led1"; |
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104 | lantiq,function = "gphy"; |
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105 | lantiq,pull = <2>; |
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106 | lantiq,open-drain = <0>; |
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107 | lantiq,output = <1>; |
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108 | }; |
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109 | phy-rst { |
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110 | lantiq,pins = "io42"; |
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111 | lantiq,pull = <0>; |
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112 | lantiq,open-drain = <0>; |
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113 | lantiq,output = <1>; |
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114 | }; |
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115 | pcie-rst { |
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116 | lantiq,pins = "io38"; |
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117 | lantiq,pull = <0>; |
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118 | lantiq,output = <1>; |
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119 | }; |
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120 | }; |
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121 | pins_spi_default: pins_spi_default { |
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122 | spi_in { |
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123 | lantiq,groups = "spi_di"; |
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124 | lantiq,function = "spi"; |
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125 | }; |
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126 | spi_out { |
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127 | lantiq,groups = "spi_do", "spi_clk", |
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128 | "spi_cs4"; |
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129 | lantiq,function = "spi"; |
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130 | lantiq,output = <1>; |
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131 | }; |
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132 | }; |
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133 | }; |
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134 | |||
135 | &pci0 { |
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136 | status = "okay"; |
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137 | gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>; |
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138 | }; |
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139 | |||
140 | &spi { |
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141 | status = "okay"; |
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142 | |||
143 | pinctrl-names = "default"; |
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144 | pinctrl-0 = <&pins_spi_default>; |
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145 | |||
146 | m25p80@4 { |
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147 | #address-cells = <1>; |
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148 | #size-cells = <1>; |
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149 | compatible = "jedec,spi-nor"; |
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150 | reg = <4 0>; |
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151 | spi-max-frequency = <33250000>; |
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152 | m25p,fast-read; |
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153 | |||
154 | partitions { |
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155 | compatible = "fixed-partitions"; |
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156 | #address-cells = <1>; |
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157 | #size-cells = <1>; |
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158 | |||
159 | partition@0 { |
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160 | reg = <0x0 0x20000>; |
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161 | label = "u-boot"; |
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162 | read-only; |
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163 | }; |
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164 | |||
165 | partition@20000 { |
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166 | reg = <0x20000 0xf90000>; |
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167 | label = "firmware"; |
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168 | }; |
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169 | |||
170 | partition@fb0000 { |
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171 | reg = <0xfb0000 0x10000>; |
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172 | label = "radioDECT"; |
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173 | read-only; |
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174 | }; |
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175 | |||
176 | partition@fc0000 { |
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177 | reg = <0xfc0000 0x10000>; |
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178 | label = "config"; |
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179 | read-only; |
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180 | }; |
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181 | |||
182 | romfile: partition@fd0000 { |
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183 | reg = <0xfd0000 0x10000>; |
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184 | label = "romfile"; |
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185 | read-only; |
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186 | }; |
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187 | |||
188 | partition@fe0000 { |
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189 | reg = <0xfe0000 0x10000>; |
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190 | label = "rom"; |
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191 | read-only; |
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192 | }; |
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193 | |||
194 | partition@ff0000 { |
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195 | reg = <0xff0000 0x10000>; |
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196 | label = "radio"; |
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197 | read-only; |
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198 | }; |
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199 | }; |
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200 | }; |
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201 | }; |
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202 | |||
203 | &usb_phy0 { |
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204 | status = "okay"; |
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205 | }; |
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206 | |||
207 | &usb_phy1 { |
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208 | status = "okay"; |
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209 | }; |
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210 | |||
211 | &usb0 { |
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212 | status = "okay"; |
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213 | vbus-supply = <&usb_vbus>; |
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214 | }; |
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215 | |||
216 | &usb1 { |
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217 | status = "okay"; |
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218 | vbus-supply = <&usb_vbus>; |
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219 | }; |