OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | #include "vr9.dtsi" |
2 | |||
3 | #include <dt-bindings/input/input.h> |
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4 | #include <dt-bindings/mips/lantiq_rcu_gphy.h> |
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5 | |||
6 | / { |
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7 | compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9"; |
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8 | |||
9 | chosen { |
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10 | bootargs = "console=ttyLTQ0,115200"; |
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11 | }; |
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12 | |||
13 | aliases { |
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14 | led-boot = &power; |
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15 | led-failsafe = &power; |
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16 | led-running = &power; |
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17 | |||
18 | led-usb = &led_usb1; |
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19 | led-usb2 = &led_usb2; |
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20 | }; |
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21 | |||
22 | memory@0 { |
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23 | reg = <0x0 0x4000000>; |
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24 | }; |
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25 | |||
26 | gpio-keys-polled { |
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27 | compatible = "gpio-keys-polled"; |
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28 | #address-cells = <1>; |
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29 | #size-cells = <0>; |
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30 | poll-interval = <100>; |
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31 | /* reset { |
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32 | label = "reset"; |
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33 | gpios = <&gpio 7 GPIO_ACTIVE_LOW>; |
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34 | linux,code = <KEY_RESTART>; |
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35 | };*/ |
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36 | paging { |
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37 | label = "paging"; |
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38 | gpios = <&gpio 11 GPIO_ACTIVE_LOW>; |
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39 | linux,code = <KEY_PHONE>; |
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40 | }; |
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41 | }; |
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42 | |||
43 | gpio-leds { |
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44 | compatible = "gpio-leds"; |
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45 | |||
46 | power: power { |
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47 | label = "easy80920:green:power"; |
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48 | gpios = <&stp 9 GPIO_ACTIVE_HIGH>; |
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49 | default-state = "keep"; |
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50 | }; |
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51 | warning { |
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52 | label = "easy80920:green:warning"; |
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53 | gpios = <&stp 22 GPIO_ACTIVE_HIGH>; |
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54 | }; |
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55 | fxs1 { |
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56 | label = "easy80920:green:fxs1"; |
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57 | gpios = <&stp 21 GPIO_ACTIVE_HIGH>; |
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58 | }; |
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59 | fxs2 { |
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60 | label = "easy80920:green:fxs2"; |
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61 | gpios = <&stp 20 GPIO_ACTIVE_HIGH>; |
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62 | }; |
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63 | fxo { |
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64 | label = "easy80920:green:fxo"; |
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65 | gpios = <&stp 19 GPIO_ACTIVE_HIGH>; |
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66 | }; |
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67 | led_usb1: usb1 { |
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68 | label = "easy80920:green:usb1"; |
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69 | gpios = <&stp 18 GPIO_ACTIVE_HIGH>; |
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70 | }; |
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71 | led_usb2: usb2 { |
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72 | label = "easy80920:green:usb2"; |
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73 | gpios = <&stp 15 GPIO_ACTIVE_HIGH>; |
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74 | }; |
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75 | sd { |
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76 | label = "easy80920:green:sd"; |
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77 | gpios = <&stp 14 GPIO_ACTIVE_HIGH>; |
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78 | }; |
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79 | wps { |
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80 | label = "easy80920:green:wps"; |
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81 | gpios = <&stp 12 GPIO_ACTIVE_HIGH>; |
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82 | }; |
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83 | }; |
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84 | |||
85 | usb_vbus: regulator-usb-vbus { |
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86 | compatible = "regulator-fixed"; |
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87 | |||
88 | regulator-name = "USB_VBUS"; |
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89 | |||
90 | regulator-min-microvolt = <5000000>; |
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91 | regulator-max-microvolt = <5000000>; |
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92 | |||
93 | gpio = <&gpio 33 GPIO_ACTIVE_HIGH>; |
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94 | enable-active-high; |
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95 | }; |
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96 | }; |
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97 | |||
98 | ð0 { |
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99 | lan: interface@0 { |
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100 | compatible = "lantiq,xrx200-pdi"; |
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101 | #address-cells = <1>; |
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102 | #size-cells = <0>; |
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103 | reg = <0>; |
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104 | lantiq,switch; |
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105 | |||
106 | ethernet@4 { |
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107 | compatible = "lantiq,xrx200-pdi-port"; |
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108 | reg = <4>; |
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109 | phy-mode = "gmii"; |
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110 | phy-handle = <&phy13>; |
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111 | }; |
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112 | ethernet@2 { |
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113 | compatible = "lantiq,xrx200-pdi-port"; |
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114 | reg = <2>; |
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115 | phy-mode = "gmii"; |
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116 | phy-handle = <&phy11>; |
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117 | }; |
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118 | ethernet@1 { |
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119 | compatible = "lantiq,xrx200-pdi-port"; |
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120 | reg = <1>; |
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121 | phy-mode = "rgmii"; |
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122 | phy-handle = <&phy1>; |
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123 | }; |
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124 | ethernet@0 { |
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125 | compatible = "lantiq,xrx200-pdi-port"; |
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126 | reg = <0>; |
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127 | phy-mode = "rgmii"; |
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128 | phy-handle = <&phy0>; |
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129 | }; |
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130 | }; |
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131 | |||
132 | wan: interface@1 { |
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133 | compatible = "lantiq,xrx200-pdi"; |
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134 | #address-cells = <1>; |
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135 | #size-cells = <0>; |
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136 | reg = <1>; |
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137 | lantiq,wan; |
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138 | |||
139 | ethernet@5 { |
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140 | compatible = "lantiq,xrx200-pdi-port"; |
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141 | reg = <5>; |
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142 | phy-mode = "rgmii"; |
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143 | phy-handle = <&phy5>; |
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144 | }; |
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145 | }; |
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146 | |||
147 | mdio@0 { |
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148 | #address-cells = <1>; |
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149 | #size-cells = <0>; |
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150 | compatible = "lantiq,xrx200-mdio"; |
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151 | reg = <0>; |
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152 | |||
153 | phy0: ethernet-phy@0 { |
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154 | reg = <0x0>; |
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155 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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156 | }; |
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157 | phy1: ethernet-phy@1 { |
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158 | reg = <0x1>; |
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159 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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160 | }; |
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161 | phy5: ethernet-phy@5 { |
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162 | reg = <0x5>; |
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163 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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164 | }; |
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165 | phy11: ethernet-phy@11 { |
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166 | reg = <0x11>; |
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167 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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168 | }; |
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169 | phy13: ethernet-phy@13 { |
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170 | reg = <0x13>; |
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171 | compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22"; |
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172 | }; |
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173 | }; |
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174 | }; |
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175 | |||
176 | &gphy0 { |
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177 | lantiq,gphy-mode = <GPHY_MODE_GE>; |
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178 | }; |
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179 | |||
180 | &gphy1 { |
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181 | lantiq,gphy-mode = <GPHY_MODE_GE>; |
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182 | }; |
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183 | |||
184 | &gpio { |
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185 | pinctrl-names = "default"; |
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186 | pinctrl-0 = <&state_default>; |
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187 | |||
188 | state_default: pinmux { |
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189 | exin3 { |
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190 | lantiq,groups = "exin3"; |
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191 | lantiq,function = "exin"; |
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192 | }; |
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193 | stp { |
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194 | lantiq,groups = "stp"; |
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195 | lantiq,function = "stp"; |
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196 | }; |
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197 | nand { |
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198 | lantiq,groups = "nand cle", "nand ale", |
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199 | "nand rd", "nand rdy"; |
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200 | lantiq,function = "ebu"; |
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201 | }; |
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202 | mdio { |
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203 | lantiq,groups = "mdio"; |
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204 | lantiq,function = "mdio"; |
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205 | }; |
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206 | pci { |
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207 | lantiq,groups = "gnt1", "req1"; |
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208 | lantiq,function = "pci"; |
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209 | }; |
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210 | conf_out { |
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211 | lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */ |
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212 | "io4", "io5", "io6", /* stp */ |
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213 | "io21", |
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214 | "io33"; |
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215 | lantiq,open-drain; |
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216 | lantiq,pull = <0>; |
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217 | lantiq,output = <1>; |
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218 | }; |
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219 | pcie-rst { |
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220 | lantiq,pins = "io38"; |
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221 | lantiq,pull = <0>; |
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222 | lantiq,output = <1>; |
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223 | }; |
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224 | conf_in { |
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225 | lantiq,pins = "io39", /* exin3 */ |
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226 | "io48"; /* nand rdy */ |
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227 | lantiq,pull = <2>; |
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228 | }; |
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229 | }; |
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230 | pins_spi_default: pins_spi_default { |
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231 | spi_in { |
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232 | lantiq,groups = "spi_di"; |
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233 | lantiq,function = "spi"; |
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234 | }; |
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235 | spi_out { |
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236 | lantiq,groups = "spi_do", "spi_clk", |
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237 | "spi_cs4"; |
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238 | lantiq,function = "spi"; |
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239 | lantiq,output = <1>; |
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240 | }; |
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241 | }; |
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242 | }; |
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243 | |||
244 | &spi { |
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245 | pinctrl-names = "default"; |
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246 | pinctrl-0 = <&pins_spi_default>; |
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247 | |||
248 | status = "okay"; |
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249 | |||
250 | m25p80@4 { |
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251 | #address-cells = <1>; |
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252 | #size-cells = <1>; |
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253 | compatible = "jedec,spi-nor"; |
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254 | reg = <4 0>; |
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255 | spi-max-frequency = <1000000>; |
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256 | |||
257 | partitions { |
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258 | compatible = "fixed-partitions"; |
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259 | #address-cells = <1>; |
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260 | #size-cells = <1>; |
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261 | |||
262 | partition@0 { |
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263 | reg = <0x0 0x20000>; |
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264 | label = "SPI (RO) U-Boot Image"; |
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265 | read-only; |
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266 | }; |
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267 | |||
268 | partition@20000 { |
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269 | reg = <0x20000 0x10000>; |
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270 | label = "ENV_MAC"; |
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271 | read-only; |
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272 | }; |
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273 | |||
274 | partition@30000 { |
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275 | reg = <0x30000 0x10000>; |
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276 | label = "DPF"; |
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277 | read-only; |
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278 | }; |
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279 | |||
280 | partition@40000 { |
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281 | reg = <0x40000 0x10000>; |
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282 | label = "NVRAM"; |
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283 | read-only; |
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284 | }; |
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285 | |||
286 | partition@500000 { |
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287 | reg = <0x50000 0x003a0000>; |
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288 | label = "kernel"; |
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289 | }; |
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290 | }; |
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291 | }; |
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292 | }; |
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293 | |||
294 | &stp { |
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295 | status = "okay"; |
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296 | |||
297 | lantiq,shadow = <0xffff>; |
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298 | lantiq,groups = <0x7>; |
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299 | lantiq,dsl = <0x3>; |
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300 | lantiq,phy1 = <0x7>; |
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301 | lantiq,phy2 = <0x7>; |
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302 | /* lantiq,rising; */ |
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303 | }; |
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304 | |||
305 | &usb_phy0 { |
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306 | status = "okay"; |
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3 | office | 307 | phy-supply = <&usb_vbus>; |
1 | office | 308 | }; |
309 | |||
310 | &usb0 { |
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311 | status = "okay"; |
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312 | }; |