OpenWrt – Blame information for rev 2

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1 office 1 #include "vr9.dtsi"
2  
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
5  
6 / {
7 compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
8  
9 chosen {
10 bootargs = "console=ttyLTQ0,115200";
11 };
12  
13 aliases {
14 led-boot = &power;
15 led-failsafe = &power;
16 led-running = &power;
17 led-upgrade = &power;
18  
19 led-usb = &led_usb1;
20 led-usb2 = &led_usb2;
21 };
22  
23 memory@0 {
24 reg = <0x0 0x4000000>;
25 };
26  
27 gpio-keys-polled {
28 compatible = "gpio-keys-polled";
29 #address-cells = <1>;
30 #size-cells = <0>;
31 poll-interval = <100>;
32 /* reset {
33 label = "reset";
34 gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_RESTART>;
36 };*/
37 paging {
38 label = "paging";
39 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
40 linux,code = <KEY_PHONE>;
41 };
42 };
43  
44 gpio-leds {
45 compatible = "gpio-leds";
46  
47 power: power {
48 label = "easy80920:green:power";
49 gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
50 default-state = "keep";
51 };
52 warning {
53 label = "easy80920:green:warning";
54 gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
55 };
56 fxs1 {
57 label = "easy80920:green:fxs1";
58 gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
59 };
60 fxs2 {
61 label = "easy80920:green:fxs2";
62 gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
63 };
64 fxo {
65 label = "easy80920:green:fxo";
66 gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
67 };
68 led_usb1: usb1 {
69 label = "easy80920:green:usb1";
70 gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
71 };
72 led_usb2: usb2 {
73 label = "easy80920:green:usb2";
74 gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
75 };
76 sd {
77 label = "easy80920:green:sd";
78 gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
79 };
80 wps {
81 label = "easy80920:green:wps";
82 gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
83 };
84 };
85  
86 usb_vbus: regulator-usb-vbus {
87 compatible = "regulator-fixed";
88  
89 regulator-name = "USB_VBUS";
90  
91 regulator-min-microvolt = <5000000>;
92 regulator-max-microvolt = <5000000>;
93  
94 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
95 enable-active-high;
96 };
97 };
98  
99 &eth0 {
100 lan: interface@0 {
101 compatible = "lantiq,xrx200-pdi";
102 #address-cells = <1>;
103 #size-cells = <0>;
104 reg = <0>;
105 lantiq,switch;
106  
107 ethernet@4 {
108 compatible = "lantiq,xrx200-pdi-port";
109 reg = <4>;
110 phy-mode = "gmii";
111 phy-handle = <&phy13>;
112 };
113 ethernet@2 {
114 compatible = "lantiq,xrx200-pdi-port";
115 reg = <2>;
116 phy-mode = "gmii";
117 phy-handle = <&phy11>;
118 };
119 ethernet@1 {
120 compatible = "lantiq,xrx200-pdi-port";
121 reg = <1>;
122 phy-mode = "rgmii";
123 phy-handle = <&phy1>;
124 };
125 ethernet@0 {
126 compatible = "lantiq,xrx200-pdi-port";
127 reg = <0>;
128 phy-mode = "rgmii";
129 phy-handle = <&phy0>;
130 };
131 };
132  
133 wan: interface@1 {
134 compatible = "lantiq,xrx200-pdi";
135 #address-cells = <1>;
136 #size-cells = <0>;
137 reg = <1>;
138 lantiq,wan;
139  
140 ethernet@5 {
141 compatible = "lantiq,xrx200-pdi-port";
142 reg = <5>;
143 phy-mode = "rgmii";
144 phy-handle = <&phy5>;
145 };
146 };
147  
148 mdio@0 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "lantiq,xrx200-mdio";
152 reg = <0>;
153  
154 phy0: ethernet-phy@0 {
155 reg = <0x0>;
156 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
157 };
158 phy1: ethernet-phy@1 {
159 reg = <0x1>;
160 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
161 };
162 phy5: ethernet-phy@5 {
163 reg = <0x5>;
164 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
165 };
166 phy11: ethernet-phy@11 {
167 reg = <0x11>;
168 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
169 };
170 phy13: ethernet-phy@13 {
171 reg = <0x13>;
172 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
173 };
174 };
175 };
176  
177 &gphy0 {
178 lantiq,gphy-mode = <GPHY_MODE_GE>;
179 };
180  
181 &gphy1 {
182 lantiq,gphy-mode = <GPHY_MODE_GE>;
183 };
184  
185 &gpio {
186 pinctrl-names = "default";
187 pinctrl-0 = <&state_default>;
188  
189 state_default: pinmux {
190 exin3 {
191 lantiq,groups = "exin3";
192 lantiq,function = "exin";
193 };
194 stp {
195 lantiq,groups = "stp";
196 lantiq,function = "stp";
197 };
198 nand {
199 lantiq,groups = "nand cle", "nand ale",
200 "nand rd", "nand rdy";
201 lantiq,function = "ebu";
202 };
203 mdio {
204 lantiq,groups = "mdio";
205 lantiq,function = "mdio";
206 };
207 pci {
208 lantiq,groups = "gnt1", "req1";
209 lantiq,function = "pci";
210 };
211 conf_out {
212 lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
213 "io4", "io5", "io6", /* stp */
214 "io21",
215 "io33";
216 lantiq,open-drain;
217 lantiq,pull = <0>;
218 lantiq,output = <1>;
219 };
220 pcie-rst {
221 lantiq,pins = "io38";
222 lantiq,pull = <0>;
223 lantiq,output = <1>;
224 };
225 conf_in {
226 lantiq,pins = "io39", /* exin3 */
227 "io48"; /* nand rdy */
228 lantiq,pull = <2>;
229 };
230 };
231 pins_spi_default: pins_spi_default {
232 spi_in {
233 lantiq,groups = "spi_di";
234 lantiq,function = "spi";
235 };
236 spi_out {
237 lantiq,groups = "spi_do", "spi_clk",
238 "spi_cs4";
239 lantiq,function = "spi";
240 lantiq,output = <1>;
241 };
242 };
243 };
244  
245 &spi {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pins_spi_default>;
248  
249 status = "okay";
250  
251 m25p80@4 {
252 #address-cells = <1>;
253 #size-cells = <1>;
254 compatible = "jedec,spi-nor";
255 reg = <4 0>;
256 spi-max-frequency = <1000000>;
257  
258 partitions {
259 compatible = "fixed-partitions";
260 #address-cells = <1>;
261 #size-cells = <1>;
262  
263 partition@0 {
264 reg = <0x0 0x20000>;
265 label = "SPI (RO) U-Boot Image";
266 read-only;
267 };
268  
269 partition@20000 {
270 reg = <0x20000 0x10000>;
271 label = "ENV_MAC";
272 read-only;
273 };
274  
275 partition@30000 {
276 reg = <0x30000 0x10000>;
277 label = "DPF";
278 read-only;
279 };
280  
281 partition@40000 {
282 reg = <0x40000 0x10000>;
283 label = "NVRAM";
284 read-only;
285 };
286  
287 partition@500000 {
288 reg = <0x50000 0x003a0000>;
289 label = "kernel";
290 };
291 };
292 };
293 };
294  
295 &stp {
296 status = "okay";
297  
298 lantiq,shadow = <0xffff>;
299 lantiq,groups = <0x7>;
300 lantiq,dsl = <0x3>;
301 lantiq,phy1 = <0x7>;
302 lantiq,phy2 = <0x7>;
303 /* lantiq,rising; */
304 };
305  
306 &usb_phy0 {
307 status = "okay";
308 };
309  
310 &usb0 {
311 status = "okay";
312 vbus-supply = <&usb_vbus>;
313 };