OpenWrt – Blame information for rev 2

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1 office 1 From patchwork Fri Dec 8 09:42:24 2017
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 Subject: [v4,06/12] clk: qcom: Add IPQ806X's HFPLLs
6 From: Sricharan R <sricharan@codeaurora.org>
7 X-Patchwork-Id: 10102047
8 Message-Id: <1512726150-7204-7-git-send-email-sricharan@codeaurora.org>
9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
10 devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
11 linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
12 viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
13 Cc: sricharan@codeaurora.org
14 Date: Fri, 8 Dec 2017 15:12:24 +0530
15  
16 From: Stephen Boyd <sboyd@codeaurora.org>
17  
18 Describe the HFPLLs present on IPQ806X devices.
19  
20 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
21 ---
22 drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++++++++++
23 1 file changed, 82 insertions(+)
24  
25 --- a/drivers/clk/qcom/gcc-ipq806x.c
26 +++ b/drivers/clk/qcom/gcc-ipq806x.c
27 @@ -30,6 +30,7 @@
28 #include "clk-pll.h"
29 #include "clk-rcg.h"
30 #include "clk-branch.h"
31 +#include "clk-hfpll.h"
32 #include "reset.h"
33  
34 static struct clk_pll pll0 = {
35 @@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = {
36 },
37 };
38  
39 +static struct hfpll_data hfpll0_data = {
40 + .mode_reg = 0x3200,
41 + .l_reg = 0x3208,
42 + .m_reg = 0x320c,
43 + .n_reg = 0x3210,
44 + .config_reg = 0x3204,
45 + .status_reg = 0x321c,
46 + .config_val = 0x7845c665,
47 + .droop_reg = 0x3214,
48 + .droop_val = 0x0108c000,
49 + .min_rate = 600000000UL,
50 + .max_rate = 1800000000UL,
51 +};
52 +
53 +static struct clk_hfpll hfpll0 = {
54 + .d = &hfpll0_data,
55 + .clkr.hw.init = &(struct clk_init_data){
56 + .parent_names = (const char *[]){ "pxo" },
57 + .num_parents = 1,
58 + .name = "hfpll0",
59 + .ops = &clk_ops_hfpll,
60 + .flags = CLK_IGNORE_UNUSED,
61 + },
62 + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
63 +};
64 +
65 +static struct hfpll_data hfpll1_data = {
66 + .mode_reg = 0x3240,
67 + .l_reg = 0x3248,
68 + .m_reg = 0x324c,
69 + .n_reg = 0x3250,
70 + .config_reg = 0x3244,
71 + .status_reg = 0x325c,
72 + .config_val = 0x7845c665,
73 + .droop_reg = 0x3314,
74 + .droop_val = 0x0108c000,
75 + .min_rate = 600000000UL,
76 + .max_rate = 1800000000UL,
77 +};
78 +
79 +static struct clk_hfpll hfpll1 = {
80 + .d = &hfpll1_data,
81 + .clkr.hw.init = &(struct clk_init_data){
82 + .parent_names = (const char *[]){ "pxo" },
83 + .num_parents = 1,
84 + .name = "hfpll1",
85 + .ops = &clk_ops_hfpll,
86 + .flags = CLK_IGNORE_UNUSED,
87 + },
88 + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
89 +};
90 +
91 +static struct hfpll_data hfpll_l2_data = {
92 + .mode_reg = 0x3300,
93 + .l_reg = 0x3308,
94 + .m_reg = 0x330c,
95 + .n_reg = 0x3310,
96 + .config_reg = 0x3304,
97 + .status_reg = 0x331c,
98 + .config_val = 0x7845c665,
99 + .droop_reg = 0x3314,
100 + .droop_val = 0x0108c000,
101 + .min_rate = 600000000UL,
102 + .max_rate = 1800000000UL,
103 +};
104 +
105 +static struct clk_hfpll hfpll_l2 = {
106 + .d = &hfpll_l2_data,
107 + .clkr.hw.init = &(struct clk_init_data){
108 + .parent_names = (const char *[]){ "pxo" },
109 + .num_parents = 1,
110 + .name = "hfpll_l2",
111 + .ops = &clk_ops_hfpll,
112 + .flags = CLK_IGNORE_UNUSED,
113 + },
114 + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
115 +};
116 +
117 static struct clk_pll pll14 = {
118 .l_reg = 0x31c4,
119 .m_reg = 0x31c8,
120 @@ -2801,6 +2880,9 @@ static struct clk_regmap *gcc_ipq806x_cl
121 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
122 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
123 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
124 + [PLL9] = &hfpll0.clkr,
125 + [PLL10] = &hfpll1.clkr,
126 + [PLL12] = &hfpll_l2.clkr,
127 };
128  
129 static const struct qcom_reset_map gcc_ipq806x_resets[] = {