OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |
2 | +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |
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3 | @@ -15,6 +15,7 @@ |
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4 | */ |
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5 | |||
6 | #include "qcom-ipq4019.dtsi" |
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7 | +#include <dt-bindings/soc/qcom,tcsr.h> |
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8 | |||
9 | / { |
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10 | model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; |
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11 | @@ -29,6 +30,32 @@ |
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12 | }; |
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13 | |||
14 | soc { |
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15 | + tcsr@194b000 { |
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16 | + /* select hostmode */ |
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17 | + compatible = "qcom,tcsr"; |
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18 | + reg = <0x194b000 0x100>; |
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19 | + qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>; |
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20 | + status = "ok"; |
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21 | + }; |
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22 | + |
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23 | + ess_tcsr@1953000 { |
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24 | + compatible = "qcom,tcsr"; |
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25 | + reg = <0x1953000 0x1000>; |
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26 | + qcom,ess-interface-select = <TCSR_ESS_PSGMII>; |
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27 | + }; |
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28 | + |
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29 | + tcsr@1949000 { |
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30 | + compatible = "qcom,tcsr"; |
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31 | + reg = <0x1949000 0x100>; |
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32 | + qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; |
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33 | + }; |
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34 | + |
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35 | + tcsr@1957000 { |
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36 | + compatible = "qcom,tcsr"; |
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37 | + reg = <0x1957000 0x100>; |
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38 | + qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; |
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39 | + }; |
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40 | + |
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41 | rng@22000 { |
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42 | status = "ok"; |
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43 | }; |
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44 | @@ -74,14 +101,6 @@ |
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45 | pinctrl-names = "default"; |
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46 | status = "ok"; |
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47 | cs-gpios = <&tlmm 54 0>; |
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48 | - |
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49 | - mx25l25635e@0 { |
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50 | - #address-cells = <1>; |
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51 | - #size-cells = <1>; |
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52 | - reg = <0>; |
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53 | - compatible = "mx25l25635e"; |
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54 | - spi-max-frequency = <24000000>; |
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55 | - }; |
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56 | }; |
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57 | |||
58 | serial@78af000 { |
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59 | @@ -110,6 +129,22 @@ |
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60 | status = "ok"; |
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61 | }; |
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62 | |||
63 | + mdio@90000 { |
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64 | + status = "okay"; |
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65 | + }; |
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66 | + |
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67 | + ess-switch@c000000 { |
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68 | + status = "okay"; |
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69 | + }; |
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70 | + |
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71 | + ess-psgmii@98000 { |
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72 | + status = "okay"; |
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73 | + }; |
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74 | + |
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75 | + edma@c080000 { |
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76 | + status = "okay"; |
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77 | + }; |
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78 | + |
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79 | usb3_ss_phy: ssphy@9a000 { |
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80 | status = "ok"; |
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81 | }; |
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82 | --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts |
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83 | +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts |
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84 | @@ -18,5 +18,73 @@ |
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85 | |||
86 | / { |
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87 | model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; |
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88 | + compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1", "qcom,ipq4019"; |
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89 | |||
90 | + memory { |
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91 | + device_type = "memory"; |
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92 | + reg = <0x80000000 0x10000000>; |
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93 | + }; |
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94 | +}; |
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95 | + |
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96 | +&blsp1_spi1 { |
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97 | + mx25l25635f@0 { |
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98 | + compatible = "mx25l25635f", "jedec,spi-nor"; |
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99 | + #address-cells = <1>; |
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100 | + #size-cells = <1>; |
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101 | + reg = <0>; |
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102 | + spi-max-frequency = <24000000>; |
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103 | + |
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104 | + SBL1@0 { |
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105 | + label = "SBL1"; |
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106 | + reg = <0x0 0x40000>; |
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107 | + read-only; |
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108 | + }; |
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109 | + MIBIB@40000 { |
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110 | + label = "MIBIB"; |
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111 | + reg = <0x40000 0x20000>; |
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112 | + read-only; |
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113 | + }; |
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114 | + QSEE@60000 { |
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115 | + label = "QSEE"; |
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116 | + reg = <0x60000 0x60000>; |
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117 | + read-only; |
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118 | + }; |
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119 | + CDT@c0000 { |
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120 | + label = "CDT"; |
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121 | + reg = <0xc0000 0x10000>; |
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122 | + read-only; |
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123 | + }; |
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124 | + DDRPARAMS@d0000 { |
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125 | + label = "DDRPARAMS"; |
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126 | + reg = <0xd0000 0x10000>; |
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127 | + read-only; |
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128 | + }; |
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129 | + APPSBLENV@e0000 { |
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130 | + label = "APPSBLENV"; |
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131 | + reg = <0xe0000 0x10000>; |
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132 | + read-only; |
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133 | + }; |
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134 | + APPSBL@f0000 { |
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135 | + label = "APPSBL"; |
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136 | + reg = <0xf0000 0x80000>; |
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137 | + read-only; |
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138 | + }; |
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139 | + ART@170000 { |
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140 | + label = "ART"; |
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141 | + reg = <0x170000 0x10000>; |
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142 | + read-only; |
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143 | + }; |
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144 | + kernel@180000 { |
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145 | + label = "kernel"; |
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146 | + reg = <0x180000 0x400000>; |
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147 | + }; |
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148 | + rootfs@580000 { |
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149 | + label = "rootfs"; |
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150 | + reg = <0x580000 0x1600000>; |
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151 | + }; |
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152 | + firmware@180000 { |
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153 | + label = "firmware"; |
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154 | + reg = <0x180000 0x1a00000>; |
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155 | + }; |
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156 | + }; |
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157 | }; |