OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From: Christian Lamparter <chunkeey@googlemail.com> |
2 | Subject: SoC: add qualcomm syscon |
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3 | --- a/drivers/soc/qcom/Makefile |
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4 | +++ b/drivers/soc/qcom/Makefile |
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5 | @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_st |
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6 | obj-$(CONFIG_QCOM_SMP2P) += smp2p.o |
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7 | obj-$(CONFIG_QCOM_SMSM) += smsm.o |
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8 | obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o |
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9 | +obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o |
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10 | --- a/drivers/soc/qcom/Kconfig |
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11 | +++ b/drivers/soc/qcom/Kconfig |
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12 | @@ -78,6 +78,13 @@ config QCOM_SMSM |
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13 | Say yes here to support the Qualcomm Shared Memory State Machine. |
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14 | The state machine is represented by bits in shared memory. |
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15 | |||
16 | +config QCOM_TCSR |
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17 | + tristate "QCOM Top Control and Status Registers" |
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18 | + depends on ARCH_QCOM |
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19 | + help |
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20 | + Say y here to enable TCSR support. The TCSR provides control |
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21 | + functions for various peripherals. |
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22 | + |
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23 | config QCOM_WCNSS_CTRL |
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24 | tristate "Qualcomm WCNSS control driver" |
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25 | depends on ARCH_QCOM |
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26 | --- /dev/null |
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27 | +++ b/drivers/soc/qcom/qcom_tcsr.c |
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28 | @@ -0,0 +1,98 @@ |
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29 | +/* |
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30 | + * Copyright (c) 2014, The Linux foundation. All rights reserved. |
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31 | + * |
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32 | + * This program is free software; you can redistribute it and/or modify |
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33 | + * it under the terms of the GNU General Public License rev 2 and |
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34 | + * only rev 2 as published by the free Software foundation. |
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35 | + * |
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36 | + * This program is distributed in the hope that it will be useful, |
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37 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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38 | + * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the |
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39 | + * GNU General Public License for more details. |
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40 | + */ |
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41 | + |
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42 | +#include <linux/clk.h> |
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43 | +#include <linux/err.h> |
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44 | +#include <linux/io.h> |
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45 | +#include <linux/module.h> |
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46 | +#include <linux/of.h> |
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47 | +#include <linux/of_platform.h> |
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48 | +#include <linux/platform_device.h> |
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49 | + |
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50 | +#define TCSR_USB_PORT_SEL 0xb0 |
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51 | +#define TCSR_USB_HSPHY_CONFIG 0xC |
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52 | + |
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53 | +#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0 |
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54 | +#define TCSR_ESS_INTERFACE_SEL_MASK 0xf |
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55 | + |
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56 | +#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0 |
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57 | +#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4 |
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58 | +#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4 |
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59 | + |
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60 | +static int tcsr_probe(struct platform_device *pdev) |
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61 | +{ |
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62 | + struct resource *res; |
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63 | + const struct device_node *node = pdev->dev.of_node; |
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64 | + void __iomem *base; |
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65 | + u32 val; |
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66 | + |
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67 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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68 | + base = devm_ioremap_resource(&pdev->dev, res); |
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69 | + if (IS_ERR(base)) |
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70 | + return PTR_ERR(base); |
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71 | + |
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72 | + if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) { |
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73 | + dev_err(&pdev->dev, "setting usb port select = %d\n", val); |
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74 | + writel(val, base + TCSR_USB_PORT_SEL); |
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75 | + } |
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76 | + |
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77 | + if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) { |
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78 | + dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val); |
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79 | + writel(val, base + TCSR_USB_HSPHY_CONFIG); |
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80 | + } |
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81 | + |
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82 | + if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) { |
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83 | + u32 tmp = 0; |
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84 | + dev_info(&pdev->dev, "setting ess interface select = %x\n", val); |
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85 | + tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET); |
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86 | + tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK); |
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87 | + tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK); |
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88 | + writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET); |
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89 | + } |
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90 | + |
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91 | + if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) { |
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92 | + dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val); |
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93 | + writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET); |
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94 | + writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET); |
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95 | + } |
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96 | + |
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97 | + if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) { |
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98 | + dev_info(&pdev->dev, |
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99 | + "setting wifi_noc_memtype_m0_m2 = %x\n", val); |
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100 | + writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2); |
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101 | + } |
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102 | + |
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103 | + return 0; |
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104 | +} |
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105 | + |
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106 | +static const struct of_device_id tcsr_dt_match[] = { |
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107 | + { .compatible = "qcom,tcsr", }, |
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108 | + { }, |
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109 | +}; |
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110 | + |
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111 | +MODULE_DEVICE_TABLE(of, tcsr_dt_match); |
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112 | + |
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113 | +static struct platform_driver tcsr_driver = { |
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114 | + .driver = { |
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115 | + .name = "tcsr", |
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116 | + .owner = THIS_MODULE, |
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117 | + .of_match_table = tcsr_dt_match, |
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118 | + }, |
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119 | + .probe = tcsr_probe, |
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120 | +}; |
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121 | + |
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122 | +module_platform_driver(tcsr_driver); |
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123 | + |
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124 | +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); |
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125 | +MODULE_DESCRIPTION("QCOM TCSR driver"); |
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126 | +MODULE_LICENSE("GPL v2"); |
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127 | --- /dev/null |
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128 | +++ b/include/dt-bindings/soc/qcom,tcsr.h |
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129 | @@ -0,0 +1,48 @@ |
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130 | +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
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131 | + * |
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132 | + * This program is free software; you can redistribute it and/or modify |
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133 | + * it under the terms of the GNU General Public License version 2 and |
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134 | + * only version 2 as published by the Free Software Foundation. |
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135 | + * |
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136 | + * This program is distributed in the hope that it will be useful, |
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137 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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138 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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139 | + * GNU General Public License for more details. |
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140 | + */ |
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141 | +#ifndef __DT_BINDINGS_QCOM_TCSR_H |
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142 | +#define __DT_BINDINGS_QCOM_TCSR_H |
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143 | + |
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144 | +#define TCSR_USB_SELECT_USB3_P0 0x1 |
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145 | +#define TCSR_USB_SELECT_USB3_P1 0x2 |
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146 | +#define TCSR_USB_SELECT_USB3_DUAL 0x3 |
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147 | + |
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148 | +/* IPQ40xx HS PHY Mode Select */ |
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149 | +#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7 |
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150 | +#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7 |
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151 | + |
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152 | +/* IPQ40xx ess interface mode select */ |
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153 | +#define TCSR_ESS_PSGMII 0 |
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154 | +#define TCSR_ESS_PSGMII_RGMII5 1 |
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155 | +#define TCSR_ESS_PSGMII_RMII0 2 |
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156 | +#define TCSR_ESS_PSGMII_RMII1 4 |
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157 | +#define TCSR_ESS_PSGMII_RMII0_RMII1 6 |
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158 | +#define TCSR_ESS_PSGMII_RGMII4 9 |
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159 | + |
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160 | +/* |
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161 | + * IPQ40xx WiFi Global Config |
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162 | + * Bit 30:AXID_EN |
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163 | + * Enable AXI master bus Axid translating to confirm all txn submitted by order |
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164 | + * Bit 24: Use locally generated socslv_wxi_bvalid |
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165 | + * 1: use locally generate socslv_wxi_bvalid for performance. |
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166 | + * 0: use SNOC socslv_wxi_bvalid. |
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167 | + */ |
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168 | +#define TCSR_WIFI_GLB_CFG 0x41000000 |
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169 | + |
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170 | +/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */ |
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171 | +#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222 |
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172 | + |
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173 | +/* TCSR A/B REG */ |
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174 | +#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0 |
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175 | +#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1 |
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176 | + |
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177 | +#endif |