OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 1fc7d5523e21ed140fed43c4dde011a3b6d9ba08 Mon Sep 17 00:00:00 2001 |
2 | From: John Crispin <john@phrozen.org> |
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3 | Date: Tue, 24 Jul 2018 14:47:55 +0200 |
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4 | Subject: [PATCH 3/3] qcom: ipq4019: add USB devicetree nodes |
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5 | |||
6 | This patch makes USB work on the Dakota EVB. |
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7 | |||
8 | Signed-off-by: John Crispin <john@phrozen.org> |
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9 | --- |
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10 | arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++ |
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11 | arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++ |
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12 | 2 files changed, 94 insertions(+) |
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13 | |||
14 | --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |
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15 | +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi |
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16 | @@ -101,5 +101,25 @@ |
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17 | wifi@a800000 { |
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18 | status = "ok"; |
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19 | }; |
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20 | + |
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21 | + usb3_ss_phy: ssphy@9a000 { |
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22 | + status = "ok"; |
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23 | + }; |
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24 | + |
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25 | + usb3_hs_phy: hsphy@a6000 { |
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26 | + status = "ok"; |
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27 | + }; |
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28 | + |
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29 | + usb3: usb3@8af8800 { |
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30 | + status = "ok"; |
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31 | + }; |
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32 | + |
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33 | + usb2_hs_phy: hsphy@a8000 { |
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34 | + status = "ok"; |
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35 | + }; |
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36 | + |
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37 | + usb2: usb2@60f8800 { |
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38 | + status = "ok"; |
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39 | + }; |
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40 | }; |
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41 | }; |
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42 | --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi |
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43 | +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi |
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44 | @@ -410,5 +410,79 @@ |
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45 | "legacy"; |
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46 | status = "disabled"; |
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47 | }; |
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48 | + |
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49 | + usb3_ss_phy: ssphy@9a000 { |
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50 | + compatible = "qcom,usb-ss-ipq4019-phy"; |
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51 | + #phy-cells = <0>; |
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52 | + reg = <0x9a000 0x800>; |
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53 | + reg-names = "phy_base"; |
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54 | + resets = <&gcc USB3_UNIPHY_PHY_ARES>; |
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55 | + reset-names = "por_rst"; |
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56 | + status = "disabled"; |
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57 | + }; |
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58 | + |
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59 | + usb3_hs_phy: hsphy@a6000 { |
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60 | + compatible = "qcom,usb-hs-ipq4019-phy"; |
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61 | + #phy-cells = <0>; |
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62 | + reg = <0xa6000 0x40>; |
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63 | + reg-names = "phy_base"; |
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64 | + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; |
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65 | + reset-names = "por_rst", "srif_rst"; |
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66 | + status = "disabled"; |
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67 | + }; |
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68 | + |
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69 | + usb3@8af8800 { |
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70 | + compatible = "qcom,dwc3"; |
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71 | + reg = <0x8af8800 0x100>; |
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72 | + #address-cells = <1>; |
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73 | + #size-cells = <1>; |
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74 | + clocks = <&gcc GCC_USB3_MASTER_CLK>, |
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75 | + <&gcc GCC_USB3_SLEEP_CLK>, |
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76 | + <&gcc GCC_USB3_MOCK_UTMI_CLK>; |
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77 | + clock-names = "master", "sleep", "mock_utmi"; |
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78 | + ranges; |
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79 | + status = "disabled"; |
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80 | + |
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81 | + dwc3@8a00000 { |
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82 | + compatible = "snps,dwc3"; |
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83 | + reg = <0x8a00000 0xf8000>; |
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84 | + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
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85 | + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; |
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86 | + phy-names = "usb2-phy", "usb3-phy"; |
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87 | + dr_mode = "host"; |
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88 | + }; |
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89 | + }; |
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90 | + |
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91 | + usb2_hs_phy: hsphy@a8000 { |
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92 | + compatible = "qcom,usb-hs-ipq4019-phy"; |
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93 | + #phy-cells = <0>; |
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94 | + reg = <0xa8000 0x40>; |
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95 | + reg-names = "phy_base"; |
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96 | + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; |
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97 | + reset-names = "por_rst", "srif_rst"; |
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98 | + status = "disabled"; |
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99 | + }; |
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100 | + |
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101 | + usb2@60f8800 { |
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102 | + compatible = "qcom,dwc3"; |
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103 | + reg = <0x60f8800 0x100>; |
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104 | + #address-cells = <1>; |
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105 | + #size-cells = <1>; |
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106 | + clocks = <&gcc GCC_USB2_MASTER_CLK>, |
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107 | + <&gcc GCC_USB2_SLEEP_CLK>, |
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108 | + <&gcc GCC_USB2_MOCK_UTMI_CLK>; |
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109 | + clock-names = "master", "sleep", "mock_utmi"; |
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110 | + ranges; |
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111 | + status = "disabled"; |
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112 | + |
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113 | + dwc3@6000000 { |
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114 | + compatible = "snps,dwc3"; |
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115 | + reg = <0x6000000 0xf8000>; |
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116 | + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
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117 | + phys = <&usb2_hs_phy>; |
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118 | + phy-names = "usb2-phy"; |
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119 | + dr_mode = "host"; |
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120 | + }; |
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121 | + }; |
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122 | }; |
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123 | }; |