OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Device Tree Source for Meraki MR33 (Stinkbug) |
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3 | * |
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4 | * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com> |
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5 | * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com> |
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6 | * |
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7 | * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427 |
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8 | * |
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9 | * This file is licensed under the terms of the GNU General Public |
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10 | * License version 2. This program is licensed "as is" without |
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11 | * any warranty of any kind, whether express or implied. |
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12 | */ |
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13 | |||
14 | #include "qcom-ipq4019.dtsi" |
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3 | office | 15 | #include "qcom-ipq4019-bus.dtsi" |
1 | office | 16 | #include <dt-bindings/gpio/gpio.h> |
17 | #include <dt-bindings/input/input.h> |
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18 | #include <dt-bindings/soc/qcom,tcsr.h> |
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19 | |||
20 | / { |
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21 | model = "Meraki MR33 Access Point"; |
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22 | compatible = "meraki,mr33", "qcom,ipq4019"; |
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23 | |||
24 | aliases { |
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25 | led-boot = &status_green; |
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26 | led-failsafe = &status_red; |
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27 | led-running = &status_green; |
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28 | led-upgrade = &power_orange; |
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29 | }; |
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30 | |||
31 | /* Do we really need this defined? */ |
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32 | memory { |
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33 | device_type = "memory"; |
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34 | reg = <0x80000000 0x10000000>; |
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35 | }; |
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36 | |||
37 | soc { |
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38 | mdio@90000 { |
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39 | status = "okay"; |
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40 | pinctrl-0 = <&mdio_pins>; |
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41 | pinctrl-names = "default"; |
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42 | /delete-node/ ethernet-phy@0; |
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43 | /delete-node/ ethernet-phy@2; |
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44 | /delete-node/ ethernet-phy@3; |
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45 | /delete-node/ ethernet-phy@4; |
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46 | }; |
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47 | |||
48 | /* It is a 56-bit counter that supplies the count to the ARM arch |
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49 | timers and without upstream driver */ |
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50 | counter@4a1000 { |
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51 | compatible = "qcom,qca-gcnt"; |
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52 | reg = <0x4a1000 0x4>; |
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53 | }; |
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54 | |||
55 | ess_tcsr@1953000 { |
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56 | compatible = "qcom,tcsr"; |
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57 | reg = <0x1953000 0x1000>; |
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58 | qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>; |
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59 | }; |
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60 | |||
61 | tcsr@1949000 { |
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62 | compatible = "qcom,tcsr"; |
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63 | reg = <0x1949000 0x100>; |
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64 | qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>; |
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65 | }; |
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66 | |||
67 | tcsr@1957000 { |
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68 | compatible = "qcom,tcsr"; |
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69 | reg = <0x1957000 0x100>; |
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70 | qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>; |
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71 | }; |
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72 | |||
3 | office | 73 | serial@78af000 { |
74 | pinctrl-0 = <&serial_0_pins>; |
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75 | pinctrl-names = "default"; |
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76 | status = "okay"; |
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77 | }; |
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78 | |||
1 | office | 79 | serial@78b0000 { |
80 | pinctrl-0 = <&serial_1_pins>; |
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81 | pinctrl-names = "default"; |
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82 | status = "okay"; |
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83 | |||
84 | bluetooth { |
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85 | compatible = "ti,cc2650"; |
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86 | enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>; |
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87 | }; |
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88 | }; |
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89 | |||
90 | crypto@8e3a000 { |
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91 | status = "okay"; |
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92 | }; |
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93 | |||
94 | watchdog@b017000 { |
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95 | status = "okay"; |
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96 | }; |
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97 | |||
98 | ess-switch@c000000 { |
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99 | switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */ |
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100 | switch_lan_bmp = <0x0>; /* lan port bitmap */ |
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101 | switch_wan_bmp = <0x10>; /* wan port bitmap */ |
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102 | }; |
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103 | |||
104 | edma@c080000 { |
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105 | qcom,single-phy; |
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106 | qcom,num_gmac = <1>; |
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107 | phy-mode = "rgmii-rxid"; |
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108 | status = "okay"; |
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109 | }; |
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110 | }; |
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111 | |||
3 | office | 112 | gpio-keys { |
1 | office | 113 | compatible = "gpio-keys"; |
114 | |||
115 | reset { |
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116 | label = "reset"; |
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117 | gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; |
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118 | linux,code = <KEY_RESTART>; |
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119 | }; |
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120 | }; |
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121 | |||
3 | office | 122 | gpio-leds { |
1 | office | 123 | compatible = "gpio-leds"; |
124 | |||
125 | power_orange: power { |
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126 | label = "mr33:orange:power"; |
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127 | gpios = <&tlmm 49 GPIO_ACTIVE_LOW>; |
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128 | panic-indicator; |
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129 | }; |
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130 | }; |
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131 | }; |
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132 | |||
133 | &blsp_dma { |
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134 | status = "okay"; |
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135 | }; |
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136 | |||
137 | &cryptobam { |
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138 | status = "okay"; |
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139 | }; |
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140 | |||
141 | &gmac0 { |
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142 | qcom,phy_mdio_addr = <1>; |
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143 | qcom,poll_required = <1>; |
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144 | vlan_tag = <0 0x20>; |
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145 | }; |
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146 | |||
3 | office | 147 | &i2c_0 { |
1 | office | 148 | pinctrl-0 = <&i2c_0_pins>; |
149 | pinctrl-names = "default"; |
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150 | status = "okay"; |
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151 | at24@50 { |
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152 | compatible = "atmel,24c64"; |
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153 | pagesize = <32>; |
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154 | reg = <0x50>; |
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155 | read-only; /* This holds our MAC & Meraki board-data */ |
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156 | }; |
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157 | }; |
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158 | |||
3 | office | 159 | &i2c_1 { |
1 | office | 160 | pinctrl-0 = <&i2c_1_pins>; |
161 | pinctrl-names = "default"; |
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162 | status = "okay"; |
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163 | |||
3 | office | 164 | lp5562@30 { |
165 | enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>; |
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1 | office | 166 | compatible = "ti,lp5562"; |
3 | office | 167 | clock-mode = /bits/8 <2>; |
1 | office | 168 | reg = <0x30>; |
169 | |||
170 | /* RGB led */ |
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171 | status_red: chan0 { |
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172 | chan-name = "mr33:red:status"; |
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173 | led-cur = /bits/ 8 <0x20>; |
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174 | max-cur = /bits/ 8 <0x60>; |
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175 | }; |
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176 | |||
177 | status_green: chan1 { |
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178 | chan-name = "mr33:green:status"; |
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179 | led-cur = /bits/ 8 <0x20>; |
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180 | max-cur = /bits/ 8 <0x60>; |
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181 | }; |
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182 | |||
183 | chan2 { |
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184 | chan-name = "mr33:blue:status"; |
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185 | led-cur = /bits/ 8 <0x20>; |
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186 | max-cur = /bits/ 8 <0x60>; |
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187 | }; |
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188 | |||
189 | chan3 { |
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190 | chan-name = "mr33:white:status"; |
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191 | led-cur = /bits/ 8 <0x20>; |
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192 | max-cur = /bits/ 8 <0x60>; |
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193 | }; |
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194 | }; |
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195 | }; |
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196 | |||
197 | &nand { |
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198 | pinctrl-0 = <&nand_pins>; |
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199 | pinctrl-names = "default"; |
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200 | status = "okay"; |
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201 | |||
202 | nand@0 { |
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203 | partitions { |
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204 | compatible = "fixed-partitions"; |
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205 | #address-cells = <1>; |
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206 | #size-cells = <1>; |
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207 | |||
208 | partition@0 { |
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209 | label = "sbl1"; |
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210 | reg = <0x000000000000 0x000000100000>; |
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211 | read-only; |
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212 | }; |
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213 | partition@1 { |
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214 | label = "mibib"; |
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215 | reg = <0x000000100000 0x000000100000>; |
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216 | read-only; |
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217 | }; |
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218 | partition@2 { |
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219 | label = "bootconfig"; |
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220 | reg = <0x000000200000 0x000000100000>; |
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221 | read-only; |
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222 | }; |
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223 | partition@3 { |
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224 | label = "qsee"; |
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225 | reg = <0x000000300000 0x000000100000>; |
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226 | read-only; |
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227 | }; |
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228 | partition@4 { |
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229 | label = "qsee_alt"; |
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230 | reg = <0x000000400000 0x000000100000>; |
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231 | read-only; |
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232 | }; |
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233 | partition@5 { |
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234 | label = "cdt"; |
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235 | reg = <0x000000500000 0x000000080000>; |
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236 | read-only; |
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237 | }; |
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238 | partition@6 { |
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239 | label = "cdt_alt"; |
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240 | reg = <0x000000580000 0x000000080000>; |
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241 | read-only; |
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242 | }; |
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243 | partition@7 { |
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244 | label = "ddrparams"; |
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245 | reg = <0x000000600000 0x000000080000>; |
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246 | read-only; |
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247 | }; |
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248 | partition@8 { |
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249 | label = "u-boot"; |
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250 | reg = <0x000000700000 0x000000200000>; |
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251 | read-only; |
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252 | }; |
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253 | partition@9 { |
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254 | label = "u-boot-backup"; |
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255 | reg = <0x000000900000 0x000000200000>; |
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256 | read-only; |
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257 | }; |
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258 | partition@10 { |
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259 | label = "ART"; |
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260 | reg = <0x000000b00000 0x000000080000>; |
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261 | read-only; |
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262 | }; |
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263 | partition@11 { |
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264 | label = "ubi"; |
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265 | reg = <0x000000c00000 0x000007000000>; |
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266 | }; |
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267 | }; |
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268 | }; |
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269 | }; |
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270 | |||
271 | &pcie0 { |
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272 | status = "okay"; |
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273 | perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>; |
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274 | wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>; |
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275 | }; |
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276 | |||
277 | &qpic_bam { |
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278 | status = "okay"; |
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279 | }; |
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280 | |||
281 | &tlmm { |
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282 | /* |
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283 | * GPIO43 should be 0/1 whenever the unit is |
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284 | * powered through PoE or AC-Adapter. |
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285 | * That said, playing with this seems to |
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286 | * reset the AP. |
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287 | */ |
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288 | |||
289 | mdio_pins: mdio_pinmux { |
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290 | mux_1 { |
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291 | pins = "gpio6"; |
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292 | function = "mdio"; |
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293 | bias-pull-up; |
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294 | }; |
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295 | mux_2 { |
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296 | pins = "gpio7"; |
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297 | function = "mdc"; |
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298 | bias-pull-up; |
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299 | }; |
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300 | }; |
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301 | |||
302 | serial_0_pins: serial_pinmux { |
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303 | mux { |
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304 | pins = "gpio16", "gpio17"; |
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305 | function = "blsp_uart0"; |
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306 | bias-disable; |
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307 | }; |
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308 | }; |
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309 | |||
310 | serial_1_pins: serial1_pinmux { |
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311 | mux { |
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312 | /* We use the i2c-0 pins for serial_1 */ |
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313 | pins = "gpio8", "gpio9"; |
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314 | function = "blsp_uart1"; |
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315 | bias-disable; |
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316 | }; |
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317 | }; |
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318 | |||
319 | i2c_0_pins: i2c_0_pinmux { |
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320 | pinmux { |
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321 | function = "blsp_i2c0"; |
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322 | pins = "gpio20", "gpio21"; |
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323 | }; |
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324 | pinconf { |
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325 | pins = "gpio20", "gpio21"; |
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326 | drive-strength = <16>; |
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327 | bias-disable; |
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328 | }; |
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329 | }; |
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330 | |||
331 | i2c_1_pins: i2c_1_pinmux { |
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332 | pinmux { |
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333 | function = "blsp_i2c1"; |
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334 | pins = "gpio34", "gpio35"; |
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335 | }; |
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336 | pinconf { |
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337 | pins = "gpio34", "gpio35"; |
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338 | drive-strength = <16>; |
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339 | bias-disable; |
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340 | }; |
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341 | }; |
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342 | |||
343 | nand_pins: nand_pins { |
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344 | /* |
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345 | * There are 18 pins. 15 pins are common between LCD and NAND. |
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346 | * The QPIC controller arbitrates between LCD and NAND. Of the |
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347 | * remaining 4, 2 are for NAND and 2 are for LCD exclusively. |
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348 | * |
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349 | * The meraki source hints that the bluetooth module claims |
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350 | * pin 52 as well. But sadly, there's no data whenever this |
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351 | * is a NAND or LCD exclusive pin or not. |
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352 | */ |
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353 | |||
354 | pullups { |
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355 | pins = "gpio52", "gpio53", "gpio58", |
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356 | "gpio59"; |
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357 | function = "qpic"; |
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358 | bias-pull-up; |
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359 | }; |
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360 | |||
361 | pulldowns { |
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362 | pins = "gpio54", "gpio55", "gpio56", |
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363 | "gpio57", "gpio60", "gpio61", |
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364 | "gpio62", "gpio63", "gpio64", |
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365 | "gpio65", "gpio66", "gpio67", |
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366 | "gpio68", "gpio69"; |
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367 | function = "qpic"; |
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368 | bias-pull-down; |
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369 | }; |
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370 | }; |
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371 | }; |
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372 | |||
373 | &wifi0 { |
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374 | status = "okay"; |
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375 | qcom,ath10k-calibration-variant = "Meraki-MR33"; |
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376 | }; |
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377 | |||
378 | &wifi1 { |
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379 | status = "okay"; |
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380 | qcom,ath10k-calibration-variant = "Meraki-MR33"; |
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381 | }; |