OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From: Gabor Juhos <juhosg@openwrt.org> |
2 | Subject: net: phy: allow to configure AR803x PHYs via platform data |
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3 | |||
4 | Add a patch for the at803x phy driver, in order to be able |
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5 | to configure some register settings via platform data. |
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6 | |||
7 | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> |
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8 | --- |
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9 | drivers/net/phy/at803x.c | 56 ++++++++++++++++++++++++++++++++ |
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10 | include/linux/platform_data/phy-at803x.h | 11 +++++++ |
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11 | 2 files changed, 67 insertions(+) |
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12 | create mode 100644 include/linux/platform_data/phy-at803x.h |
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13 | |||
14 | --- a/drivers/net/phy/at803x.c |
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15 | +++ b/drivers/net/phy/at803x.c |
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16 | @@ -12,12 +12,14 @@ |
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17 | */ |
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18 | |||
19 | #include <linux/phy.h> |
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20 | +#include <linux/mdio.h> |
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21 | #include <linux/module.h> |
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22 | #include <linux/string.h> |
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23 | #include <linux/netdevice.h> |
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24 | #include <linux/etherdevice.h> |
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25 | #include <linux/of_gpio.h> |
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26 | #include <linux/gpio/consumer.h> |
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27 | +#include <linux/platform_data/phy-at803x.h> |
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28 | |||
29 | #define AT803X_INTR_ENABLE 0x12 |
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30 | #define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15) |
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31 | @@ -45,6 +47,11 @@ |
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32 | #define AT803X_REG_CHIP_CONFIG 0x1f |
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33 | #define AT803X_BT_BX_REG_SEL 0x8000 |
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34 | |||
35 | +#define AT803X_PCS_SMART_EEE_CTRL3 0x805D |
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36 | +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3 |
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37 | +#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12 |
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38 | +#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8) |
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39 | + |
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40 | #define AT803X_DEBUG_ADDR 0x1D |
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41 | #define AT803X_DEBUG_DATA 0x1E |
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42 | |||
43 | @@ -72,6 +79,7 @@ MODULE_LICENSE("GPL"); |
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44 | struct at803x_priv { |
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45 | bool phy_reset:1; |
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46 | struct gpio_desc *gpiod_reset; |
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47 | + int prev_speed; |
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48 | }; |
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49 | |||
50 | struct at803x_context { |
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51 | @@ -276,8 +284,16 @@ does_not_require_reset_workaround: |
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52 | return 0; |
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53 | } |
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54 | |||
55 | +static void at803x_disable_smarteee(struct phy_device *phydev) |
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56 | +{ |
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57 | + phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3, |
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58 | + 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT); |
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59 | + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); |
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60 | +} |
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61 | + |
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62 | static int at803x_config_init(struct phy_device *phydev) |
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63 | { |
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64 | + struct at803x_platform_data *pdata; |
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65 | int ret; |
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66 | |||
67 | ret = genphy_config_init(phydev); |
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68 | @@ -298,6 +314,26 @@ static int at803x_config_init(struct phy |
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69 | return ret; |
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70 | } |
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71 | |||
72 | + pdata = dev_get_platdata(&phydev->mdio.dev); |
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73 | + if (pdata) { |
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74 | + if (pdata->disable_smarteee) |
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75 | + at803x_disable_smarteee(phydev); |
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76 | + |
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77 | + if (pdata->enable_rgmii_rx_delay) |
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78 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0, |
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79 | + AT803X_DEBUG_RX_CLK_DLY_EN); |
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80 | + else |
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81 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, |
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82 | + AT803X_DEBUG_RX_CLK_DLY_EN, 0); |
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83 | + |
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84 | + if (pdata->enable_rgmii_tx_delay) |
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85 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, |
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86 | + AT803X_DEBUG_TX_CLK_DLY_EN); |
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87 | + else |
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88 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, |
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89 | + AT803X_DEBUG_TX_CLK_DLY_EN, 0); |
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90 | + } |
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91 | + |
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92 | return 0; |
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93 | } |
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94 | |||
95 | @@ -335,6 +371,8 @@ static int at803x_config_intr(struct phy |
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96 | static void at803x_link_change_notify(struct phy_device *phydev) |
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97 | { |
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98 | struct at803x_priv *priv = phydev->priv; |
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99 | + struct at803x_platform_data *pdata; |
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100 | + pdata = dev_get_platdata(&phydev->mdio.dev); |
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101 | |||
102 | /* |
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103 | * Conduct a hardware reset for AT8030/2 every time a link loss is |
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104 | @@ -363,6 +401,24 @@ static void at803x_link_change_notify(st |
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105 | } else { |
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106 | priv->phy_reset = false; |
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107 | } |
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108 | + if (pdata && pdata->fixup_rgmii_tx_delay && |
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109 | + phydev->speed != priv->prev_speed) { |
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110 | + switch (phydev->speed) { |
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111 | + case SPEED_10: |
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112 | + case SPEED_100: |
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113 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0, |
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114 | + AT803X_DEBUG_TX_CLK_DLY_EN); |
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115 | + break; |
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116 | + case SPEED_1000: |
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117 | + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, |
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118 | + AT803X_DEBUG_TX_CLK_DLY_EN, 0); |
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119 | + break; |
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120 | + default: |
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121 | + break; |
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122 | + } |
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123 | + |
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124 | + priv->prev_speed = phydev->speed; |
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125 | + } |
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126 | } |
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127 | |||
128 | static int at803x_aneg_done(struct phy_device *phydev) |
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129 | --- /dev/null |
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130 | +++ b/include/linux/platform_data/phy-at803x.h |
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131 | @@ -0,0 +1,11 @@ |
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132 | +#ifndef _PHY_AT803X_PDATA_H |
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133 | +#define _PHY_AT803X_PDATA_H |
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134 | + |
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135 | +struct at803x_platform_data { |
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136 | + int disable_smarteee:1; |
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137 | + int enable_rgmii_tx_delay:1; |
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138 | + int enable_rgmii_rx_delay:1; |
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139 | + int fixup_rgmii_tx_delay:1; |
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140 | +}; |
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141 | + |
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142 | +#endif /* _PHY_AT803X_PDATA_H */ |