OpenWrt – Blame information for rev 2
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1 | office | 1 | From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001 |
2 | From: Hauke Mehrtens <hauke@hauke-m.de> |
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3 | Date: Sun, 23 Dec 2018 18:06:53 +0100 |
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4 | Subject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo |
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5 | |||
6 | Many MIPS CPUs have optional CPU features which are not activates for |
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7 | all CPU cores. Print the CPU options which are implemented in the core |
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8 | in /proc/cpuinfo. This makes it possible to see what features are |
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9 | supported and which are not supported. This should cover all standard |
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10 | MIPS extensions, before it only printed information about the main MIPS |
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11 | ASEs. |
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12 | |||
13 | Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> |
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14 | --- |
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15 | arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++ |
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16 | 1 file changed, 116 insertions(+) |
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17 | |||
18 | --- a/arch/mips/kernel/proc.c |
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19 | +++ b/arch/mips/kernel/proc.c |
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20 | @@ -128,6 +128,114 @@ static int show_cpuinfo(struct seq_file |
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21 | seq_printf(m, "micromips kernel\t: %s\n", |
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22 | (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); |
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23 | } |
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24 | + |
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25 | + seq_printf(m, "Options implemented\t:"); |
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26 | + if (cpu_has_tlb) |
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27 | + seq_printf(m, "%s", " tlb"); |
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28 | + if (cpu_has_ftlb) |
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29 | + seq_printf(m, "%s", " ftlb"); |
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30 | + if (cpu_has_tlbinv) |
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31 | + seq_printf(m, "%s", " tlbinv"); |
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32 | + if (cpu_has_segments) |
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33 | + seq_printf(m, "%s", " segments"); |
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34 | + if (cpu_has_rixiex) |
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35 | + seq_printf(m, "%s", " rixiex"); |
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36 | + if (cpu_has_ldpte) |
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37 | + seq_printf(m, "%s", " ldpte"); |
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38 | + if (cpu_has_maar) |
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39 | + seq_printf(m, "%s", " maar"); |
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40 | + if (cpu_has_rw_llb) |
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41 | + seq_printf(m, "%s", " rw_llb"); |
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42 | + if (cpu_has_4kex) |
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43 | + seq_printf(m, "%s", " 4kex"); |
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44 | + if (cpu_has_3k_cache) |
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45 | + seq_printf(m, "%s", " 3k_cache"); |
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46 | + if (cpu_has_4k_cache) |
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47 | + seq_printf(m, "%s", " 4k_cache"); |
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48 | + if (cpu_has_6k_cache) |
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49 | + seq_printf(m, "%s", " 6k_cache"); |
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50 | + if (cpu_has_8k_cache) |
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51 | + seq_printf(m, "%s", " 8k_cache"); |
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52 | + if (cpu_has_tx39_cache) |
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53 | + seq_printf(m, "%s", " tx39_cache"); |
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54 | + if (cpu_has_octeon_cache) |
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55 | + seq_printf(m, "%s", " octeon_cache"); |
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56 | + if (cpu_has_fpu) |
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57 | + seq_printf(m, "%s", " fpu"); |
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58 | + if (cpu_has_32fpr) |
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59 | + seq_printf(m, "%s", " 32fpr"); |
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60 | + if (cpu_has_cache_cdex_p) |
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61 | + seq_printf(m, "%s", " cache_cdex_p"); |
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62 | + if (cpu_has_cache_cdex_s) |
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63 | + seq_printf(m, "%s", " cache_cdex_s"); |
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64 | + if (cpu_has_prefetch) |
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65 | + seq_printf(m, "%s", " prefetch"); |
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66 | + if (cpu_has_mcheck) |
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67 | + seq_printf(m, "%s", " mcheck"); |
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68 | + if (cpu_has_ejtag) |
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69 | + seq_printf(m, "%s", " ejtag"); |
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70 | + if (cpu_has_llsc) |
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71 | + seq_printf(m, "%s", " llsc"); |
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72 | + if (cpu_has_bp_ghist) |
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73 | + seq_printf(m, "%s", " bp_ghist"); |
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74 | + if (cpu_has_guestctl0ext) |
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75 | + seq_printf(m, "%s", " guestctl0ext"); |
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76 | + if (cpu_has_guestctl1) |
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77 | + seq_printf(m, "%s", " guestctl1"); |
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78 | + if (cpu_has_guestctl2) |
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79 | + seq_printf(m, "%s", " guestctl2"); |
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80 | + if (cpu_has_guestid) |
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81 | + seq_printf(m, "%s", " guestid"); |
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82 | + if (cpu_has_drg) |
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83 | + seq_printf(m, "%s", " drg"); |
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84 | + if (cpu_has_rixi) |
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85 | + seq_printf(m, "%s", " rixi"); |
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86 | + if (cpu_has_lpa) |
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87 | + seq_printf(m, "%s", " lpa"); |
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88 | + if (cpu_has_mvh) |
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89 | + seq_printf(m, "%s", " mvh"); |
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90 | + if (cpu_has_vtag_icache) |
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91 | + seq_printf(m, "%s", " vtag_icache"); |
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92 | + if (cpu_has_dc_aliases) |
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93 | + seq_printf(m, "%s", " dc_aliases"); |
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94 | + if (cpu_has_ic_fills_f_dc) |
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95 | + seq_printf(m, "%s", " ic_fills_f_dc"); |
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96 | + if (cpu_has_pindexed_dcache) |
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97 | + seq_printf(m, "%s", " pindexed_dcache"); |
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98 | + if (cpu_has_userlocal) |
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99 | + seq_printf(m, "%s", " userlocal"); |
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100 | + if (cpu_has_nofpuex) |
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101 | + seq_printf(m, "%s", " nofpuex"); |
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102 | + if (cpu_has_vint) |
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103 | + seq_printf(m, "%s", " vint"); |
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104 | + if (cpu_has_veic) |
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105 | + seq_printf(m, "%s", " veic"); |
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106 | + if (cpu_has_inclusive_pcaches) |
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107 | + seq_printf(m, "%s", " inclusive_pcaches"); |
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108 | + if (cpu_has_perf_cntr_intr_bit) |
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109 | + seq_printf(m, "%s", " perf_cntr_intr_bit"); |
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110 | + if (cpu_has_fre) |
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111 | + seq_printf(m, "%s", " fre"); |
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112 | + if (cpu_has_cdmm) |
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113 | + seq_printf(m, "%s", " cdmm"); |
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114 | + if (cpu_has_small_pages) |
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115 | + seq_printf(m, "%s", " small_pages"); |
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116 | + if (cpu_has_nan_legacy) |
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117 | + seq_printf(m, "%s", " nan_legacy"); |
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118 | + if (cpu_has_nan_2008) |
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119 | + seq_printf(m, "%s", " nan_2008"); |
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120 | + if (cpu_has_ebase_wg) |
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121 | + seq_printf(m, "%s", " ebase_wg"); |
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122 | + if (cpu_has_badinstr) |
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123 | + seq_printf(m, "%s", " badinstr"); |
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124 | + if (cpu_has_badinstrp) |
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125 | + seq_printf(m, "%s", " badinstrp"); |
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126 | + if (cpu_has_contextconfig) |
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127 | + seq_printf(m, "%s", " contextconfig"); |
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128 | + if (cpu_has_perf) |
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129 | + seq_printf(m, "%s", " perf"); |
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130 | + seq_printf(m, "\n"); |
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131 | + |
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132 | seq_printf(m, "shadow register sets\t: %d\n", |
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133 | cpu_data[n].srsets); |
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134 | seq_printf(m, "kscratch registers\t: %d\n", |