OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/drivers/bcma/driver_chipcommon.c |
2 | +++ b/drivers/bcma/driver_chipcommon.c |
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3 | @@ -15,6 +15,8 @@ |
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4 | #include <linux/platform_device.h> |
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5 | #include <linux/bcma/bcma.h> |
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6 | |||
7 | +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc); |
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8 | + |
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9 | static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, |
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10 | u32 mask, u32 value) |
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11 | { |
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12 | @@ -113,8 +115,37 @@ int bcma_chipco_watchdog_register(struct |
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13 | return 0; |
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14 | } |
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15 | |||
16 | +static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc) |
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17 | +{ |
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18 | + struct bcma_bus *bus = cc->core->bus; |
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19 | + |
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20 | + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { |
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21 | + case BCMA_CC_FLASHT_STSER: |
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22 | + case BCMA_CC_FLASHT_ATSER: |
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23 | + bcma_debug(bus, "Found serial flash\n"); |
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24 | + bcma_sflash_init(cc); |
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25 | + break; |
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26 | + case BCMA_CC_FLASHT_PARA: |
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27 | + bcma_debug(bus, "Found parallel flash\n"); |
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28 | + bcma_pflash_init(cc); |
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29 | + break; |
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30 | + default: |
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31 | + bcma_err(bus, "Flash type not supported\n"); |
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32 | + } |
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33 | + |
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34 | + if (cc->core->id.rev == 38 || |
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35 | + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { |
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36 | + if (cc->capabilities & BCMA_CC_CAP_NFLASH) { |
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37 | + bcma_debug(bus, "Found NAND flash\n"); |
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38 | + bcma_nflash_init(cc); |
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39 | + } |
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40 | + } |
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41 | +} |
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42 | + |
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43 | void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) |
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44 | { |
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45 | + struct bcma_bus *bus = cc->core->bus; |
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46 | + |
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47 | if (cc->early_setup_done) |
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48 | return; |
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49 | |||
50 | @@ -129,6 +160,12 @@ void bcma_core_chipcommon_early_init(str |
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51 | if (cc->capabilities & BCMA_CC_CAP_PMU) |
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52 | bcma_pmu_early_init(cc); |
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53 | |||
54 | + if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC) |
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55 | + bcma_chipco_serial_init(cc); |
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56 | + |
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57 | + if (bus->hosttype == BCMA_HOSTTYPE_SOC) |
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58 | + bcma_core_chipcommon_flash_detect(cc); |
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59 | + |
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60 | cc->early_setup_done = true; |
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61 | } |
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62 | |||
63 | @@ -185,11 +222,12 @@ u32 bcma_chipco_watchdog_timer_set(struc |
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64 | ticks = 2; |
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65 | else if (ticks > maxt) |
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66 | ticks = maxt; |
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67 | - bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); |
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68 | + bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); |
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69 | } else { |
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70 | struct bcma_bus *bus = cc->core->bus; |
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71 | |||
72 | if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 && |
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73 | + bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 && |
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74 | bus->chipinfo.id != BCMA_CHIP_ID_BCM53018) |
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75 | bcma_core_set_clockmode(cc->core, |
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76 | ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC); |
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77 | @@ -314,9 +352,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm |
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78 | return res; |
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79 | } |
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80 | |||
81 | -#ifdef CONFIG_BCMA_DRIVER_MIPS |
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82 | -void bcma_chipco_serial_init(struct bcma_drv_cc *cc) |
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83 | +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc) |
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84 | { |
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85 | +#if IS_BUILTIN(CONFIG_BCM47XX) |
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86 | unsigned int irq; |
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87 | u32 baud_base; |
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88 | u32 i; |
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89 | @@ -358,5 +396,5 @@ void bcma_chipco_serial_init(struct bcma |
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90 | ports[i].baud_base = baud_base; |
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91 | ports[i].reg_shift = 0; |
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92 | } |
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93 | +#endif /* CONFIG_BCM47XX */ |
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94 | } |
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95 | -#endif /* CONFIG_BCMA_DRIVER_MIPS */ |
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96 | --- a/drivers/bcma/driver_chipcommon_pmu.c |
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97 | +++ b/drivers/bcma/driver_chipcommon_pmu.c |
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98 | @@ -15,44 +15,44 @@ |
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99 | |||
100 | u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) |
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101 | { |
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102 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); |
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103 | - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); |
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104 | - return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); |
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105 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset); |
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106 | + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR); |
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107 | + return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA); |
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108 | } |
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109 | EXPORT_SYMBOL_GPL(bcma_chipco_pll_read); |
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110 | |||
111 | void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) |
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112 | { |
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113 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); |
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114 | - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); |
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115 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); |
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116 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset); |
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117 | + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR); |
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118 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value); |
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119 | } |
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120 | EXPORT_SYMBOL_GPL(bcma_chipco_pll_write); |
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121 | |||
122 | void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, |
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123 | u32 set) |
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124 | { |
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125 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); |
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126 | - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); |
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127 | - bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set); |
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128 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset); |
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129 | + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR); |
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130 | + bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set); |
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131 | } |
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132 | EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset); |
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133 | |||
134 | void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, |
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135 | u32 offset, u32 mask, u32 set) |
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136 | { |
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137 | - bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset); |
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138 | - bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); |
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139 | - bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set); |
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140 | + bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset); |
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141 | + bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR); |
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142 | + bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set); |
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143 | } |
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144 | EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset); |
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145 | |||
146 | void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, |
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147 | u32 set) |
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148 | { |
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149 | - bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset); |
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150 | - bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR); |
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151 | - bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set); |
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152 | + bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset); |
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153 | + bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR); |
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154 | + bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set); |
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155 | } |
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156 | EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); |
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157 | |||
158 | @@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma |
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159 | { |
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160 | u32 ilp_ctl, alp_hz; |
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161 | |||
162 | - if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) & |
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163 | + if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) & |
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164 | BCMA_CC_PMU_STAT_EXT_LPO_AVAIL)) |
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165 | return 0; |
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166 | |||
167 | - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, |
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168 | - BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT)); |
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169 | + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, |
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170 | + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT)); |
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171 | usleep_range(1000, 2000); |
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172 | |||
173 | - ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ); |
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174 | + ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ); |
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175 | ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK; |
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176 | |||
177 | - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0); |
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178 | + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0); |
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179 | |||
180 | alp_hz = ilp_ctl * 32768 / 4; |
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181 | return (alp_hz + 50000) / 100000 * 100; |
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182 | @@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b |
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183 | mask = (u32)~(BCMA_RES_4314_HT_AVAIL | |
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184 | BCMA_RES_4314_MACPHY_CLK_AVAIL); |
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185 | |||
186 | - bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask); |
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187 | - bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask); |
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188 | + bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask); |
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189 | + bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask); |
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190 | bcma_wait_value(cc->core, BCMA_CLKCTLST, |
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191 | BCMA_CLKCTLST_HAVEHT, 0, 20000); |
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192 | break; |
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193 | @@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b |
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194 | |||
195 | /* Flush */ |
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196 | if (cc->pmu.rev >= 2) |
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197 | - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD); |
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198 | + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD); |
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199 | |||
200 | /* TODO: Do we need to update OTP? */ |
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201 | } |
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202 | @@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru |
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203 | |||
204 | /* Set the resource masks. */ |
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205 | if (min_msk) |
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206 | - bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); |
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207 | + bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); |
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208 | if (max_msk) |
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209 | - bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); |
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210 | + bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); |
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211 | |||
212 | /* |
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213 | * Add some delay; allow resources to come up and settle. |
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214 | @@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct |
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215 | |||
216 | void bcma_pmu_early_init(struct bcma_drv_cc *cc) |
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217 | { |
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218 | + struct bcma_bus *bus = cc->core->bus; |
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219 | u32 pmucap; |
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220 | |||
221 | - pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); |
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222 | + if (cc->core->id.rev >= 35 && |
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223 | + cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) { |
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224 | + cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU); |
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225 | + if (!cc->pmu.core) |
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226 | + bcma_warn(bus, "Couldn't find expected PMU core"); |
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227 | + } |
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228 | + if (!cc->pmu.core) |
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229 | + cc->pmu.core = cc->core; |
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230 | + |
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231 | + pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP); |
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232 | cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); |
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233 | |||
234 | - bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", |
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235 | - cc->pmu.rev, pmucap); |
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236 | + bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev, |
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237 | + pmucap); |
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238 | } |
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239 | |||
240 | void bcma_pmu_init(struct bcma_drv_cc *cc) |
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241 | { |
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242 | if (cc->pmu.rev == 1) |
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243 | - bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, |
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244 | - ~BCMA_CC_PMU_CTL_NOILPONW); |
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245 | + bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL, |
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246 | + ~BCMA_CC_PMU_CTL_NOILPONW); |
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247 | else |
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248 | - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, |
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249 | - BCMA_CC_PMU_CTL_NOILPONW); |
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250 | + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, |
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251 | + BCMA_CC_PMU_CTL_NOILPONW); |
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252 | |||
253 | bcma_pmu_pll_init(cc); |
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254 | bcma_pmu_resources_init(cc); |
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255 | @@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d |
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256 | static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, |
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257 | u32 value) |
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258 | { |
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259 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); |
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260 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); |
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261 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset); |
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262 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value); |
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263 | } |
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264 | |||
265 | void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) |
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266 | @@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct |
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267 | bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0; |
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268 | |||
269 | /* RMW only the P1 divider */ |
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270 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, |
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271 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, |
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272 | BCMA_CC_PMU_PLL_CTL0 + phypll_offset); |
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273 | - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); |
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274 | + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA); |
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275 | tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK)); |
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276 | tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT); |
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277 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); |
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278 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp); |
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279 | |||
280 | /* RMW only the int feedback divider */ |
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281 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, |
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282 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, |
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283 | BCMA_CC_PMU_PLL_CTL2 + phypll_offset); |
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284 | - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); |
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285 | + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA); |
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286 | tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK); |
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287 | tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; |
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288 | - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); |
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289 | + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp); |
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290 | |||
291 | tmp = BCMA_CC_PMU_CTL_PLL_UPD; |
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292 | break; |
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293 | @@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct |
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294 | break; |
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295 | } |
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296 | |||
297 | - tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL); |
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298 | - bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp); |
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299 | + tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL); |
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300 | + bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp); |
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301 | } |
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302 | EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate); |
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303 | --- a/drivers/bcma/driver_chipcommon_sflash.c |
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304 | +++ b/drivers/bcma/driver_chipcommon_sflash.c |
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305 | @@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc |
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306 | { "M25P32", 0x15, 0x10000, 64, }, |
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307 | { "M25P64", 0x16, 0x10000, 128, }, |
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308 | { "M25FL128", 0x17, 0x10000, 256, }, |
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309 | + { "MX25L25635F", 0x18, 0x10000, 512, }, |
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310 | { NULL }, |
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311 | }; |
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312 | |||
313 | --- a/drivers/bcma/scan.c |
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314 | +++ b/drivers/bcma/scan.c |
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315 | @@ -98,6 +98,9 @@ static const struct bcma_device_id_name |
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316 | { BCMA_CORE_SHIM, "SHIM" }, |
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317 | { BCMA_CORE_PCIE2, "PCIe Gen2" }, |
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318 | { BCMA_CORE_ARM_CR4, "ARM CR4" }, |
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319 | + { BCMA_CORE_GCI, "GCI" }, |
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320 | + { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" }, |
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321 | + { BCMA_CORE_ARM_CA7, "ARM CA7" }, |
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322 | { BCMA_CORE_DEFAULT, "Default" }, |
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323 | }; |
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324 | |||
325 | @@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm |
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326 | switch (core->id.id) { |
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327 | case BCMA_CORE_4706_MAC_GBIT_COMMON: |
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328 | case BCMA_CORE_NS_CHIPCOMMON_B: |
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329 | + case BCMA_CORE_PMU: |
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330 | + case BCMA_CORE_GCI: |
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331 | /* Not used yet: case BCMA_CORE_OOB_ROUTER: */ |
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332 | break; |
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333 | default: |
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334 | --- a/drivers/net/wireless/b43/main.c |
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335 | +++ b/drivers/net/wireless/b43/main.c |
||
336 | @@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str |
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337 | case B43_BUS_BCMA: |
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338 | bcma_cc = &dev->dev->bdev->bus->drv_cc; |
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339 | |||
340 | - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0); |
||
341 | - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4); |
||
342 | - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4); |
||
343 | - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4); |
||
344 | + bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0); |
||
345 | + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); |
||
346 | + bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4); |
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347 | + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4); |
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348 | break; |
||
349 | #endif |
||
350 | #ifdef CONFIG_B43_SSB |
||
351 | --- a/include/linux/bcma/bcma.h |
||
352 | +++ b/include/linux/bcma/bcma.h |
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353 | @@ -151,6 +151,8 @@ struct bcma_host_ops { |
||
354 | #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */ |
||
355 | #define BCMA_CORE_USB30_DEV 0x83D |
||
356 | #define BCMA_CORE_ARM_CR4 0x83E |
||
357 | +#define BCMA_CORE_GCI 0x840 |
||
358 | +#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */ |
||
359 | #define BCMA_CORE_ARM_CA7 0x847 |
||
360 | #define BCMA_CORE_SYS_MEM 0x849 |
||
361 | #define BCMA_CORE_DEFAULT 0xFFF |
||
362 | @@ -200,6 +202,7 @@ struct bcma_host_ops { |
||
363 | #define BCMA_PKG_ID_BCM4707 1 |
||
364 | #define BCMA_PKG_ID_BCM4708 2 |
||
365 | #define BCMA_PKG_ID_BCM4709 0 |
||
366 | +#define BCMA_CHIP_ID_BCM47094 53030 |
||
367 | #define BCMA_CHIP_ID_BCM53018 53018 |
||
368 | |||
369 | /* Board types (on PCI usually equals to the subsystem dev id) */ |
||
370 | --- a/include/linux/bcma/bcma_driver_chipcommon.h |
||
371 | +++ b/include/linux/bcma/bcma_driver_chipcommon.h |
||
372 | @@ -217,6 +217,11 @@ |
||
373 | #define BCMA_CC_CLKDIV_JTAG_SHIFT 8 |
||
374 | #define BCMA_CC_CLKDIV_UART 0x000000FF |
||
375 | #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */ |
||
376 | +#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001 |
||
377 | +#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002 |
||
378 | +#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004 |
||
379 | +#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */ |
||
380 | +#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040 |
||
381 | #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ |
||
382 | #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ |
||
383 | #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ |
||
384 | @@ -351,12 +356,12 @@ |
||
385 | #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ |
||
386 | #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */ |
||
387 | #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */ |
||
388 | -#define BCMA_CC_CHIPCTL_ADDR 0x0650 |
||
389 | -#define BCMA_CC_CHIPCTL_DATA 0x0654 |
||
390 | -#define BCMA_CC_REGCTL_ADDR 0x0658 |
||
391 | -#define BCMA_CC_REGCTL_DATA 0x065C |
||
392 | -#define BCMA_CC_PLLCTL_ADDR 0x0660 |
||
393 | -#define BCMA_CC_PLLCTL_DATA 0x0664 |
||
394 | +#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650 |
||
395 | +#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654 |
||
396 | +#define BCMA_CC_PMU_REGCTL_ADDR 0x0658 |
||
397 | +#define BCMA_CC_PMU_REGCTL_DATA 0x065C |
||
398 | +#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660 |
||
399 | +#define BCMA_CC_PMU_PLLCTL_DATA 0x0664 |
||
400 | #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */ |
||
401 | #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */ |
||
402 | #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF |
||
403 | @@ -566,17 +571,16 @@ |
||
404 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) |
||
405 | */ |
||
406 | struct bcma_chipcommon_pmu { |
||
407 | + struct bcma_device *core; /* Can be separated core or just ChipCommon one */ |
||
408 | u8 rev; /* PMU revision */ |
||
409 | u32 crystalfreq; /* The active crystal frequency (in kHz) */ |
||
410 | }; |
||
411 | |||
412 | -#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
413 | +#ifdef CONFIG_BCMA_PFLASH |
||
414 | struct bcma_pflash { |
||
415 | bool present; |
||
416 | - u8 buswidth; |
||
417 | - u32 window; |
||
418 | - u32 window_size; |
||
419 | }; |
||
420 | +#endif |
||
421 | |||
422 | #ifdef CONFIG_BCMA_SFLASH |
||
423 | struct bcma_sflash { |
||
424 | @@ -602,6 +606,7 @@ struct bcma_nflash { |
||
425 | }; |
||
426 | #endif |
||
427 | |||
428 | +#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
429 | struct bcma_serial_port { |
||
430 | void *regs; |
||
431 | unsigned long clockspeed; |
||
432 | @@ -621,8 +626,9 @@ struct bcma_drv_cc { |
||
433 | /* Fast Powerup Delay constant */ |
||
434 | u16 fast_pwrup_delay; |
||
435 | struct bcma_chipcommon_pmu pmu; |
||
436 | -#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
437 | +#ifdef CONFIG_BCMA_PFLASH |
||
438 | struct bcma_pflash pflash; |
||
439 | +#endif |
||
440 | #ifdef CONFIG_BCMA_SFLASH |
||
441 | struct bcma_sflash sflash; |
||
442 | #endif |
||
443 | @@ -630,6 +636,7 @@ struct bcma_drv_cc { |
||
444 | struct bcma_nflash nflash; |
||
445 | #endif |
||
446 | |||
447 | +#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
448 | int nr_serial_ports; |
||
449 | struct bcma_serial_port serial_ports[4]; |
||
450 | #endif /* CONFIG_BCMA_DRIVER_MIPS */ |
||
451 | @@ -663,6 +670,19 @@ struct bcma_drv_cc_b { |
||
452 | #define bcma_cc_maskset32(cc, offset, mask, set) \ |
||
453 | bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) |
||
454 | |||
455 | +/* PMU registers access */ |
||
456 | +#define bcma_pmu_read32(cc, offset) \ |
||
457 | + bcma_read32((cc)->pmu.core, offset) |
||
458 | +#define bcma_pmu_write32(cc, offset, val) \ |
||
459 | + bcma_write32((cc)->pmu.core, offset, val) |
||
460 | + |
||
461 | +#define bcma_pmu_mask32(cc, offset, mask) \ |
||
462 | + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask)) |
||
463 | +#define bcma_pmu_set32(cc, offset, set) \ |
||
464 | + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set)) |
||
465 | +#define bcma_pmu_maskset32(cc, offset, mask, set) \ |
||
466 | + bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set)) |
||
467 | + |
||
468 | extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks); |
||
469 | |||
470 | extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc); |
||
471 | --- a/drivers/bcma/bcma_private.h |
||
472 | +++ b/drivers/bcma/bcma_private.h |
||
473 | @@ -44,10 +44,6 @@ int bcma_sprom_get(struct bcma_bus *bus) |
||
474 | void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc); |
||
475 | void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); |
||
476 | void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); |
||
477 | -#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
478 | -void bcma_chipco_serial_init(struct bcma_drv_cc *cc); |
||
479 | -extern struct platform_device bcma_pflash_dev; |
||
480 | -#endif /* CONFIG_BCMA_DRIVER_MIPS */ |
||
481 | |||
482 | /* driver_chipcommon_b.c */ |
||
483 | int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb); |
||
484 | @@ -59,6 +55,21 @@ void bcma_pmu_init(struct bcma_drv_cc *c |
||
485 | u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc); |
||
486 | u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc); |
||
487 | |||
488 | +/************************************************** |
||
489 | + * driver_chipcommon_sflash.c |
||
490 | + **************************************************/ |
||
491 | + |
||
492 | +#ifdef CONFIG_BCMA_PFLASH |
||
493 | +extern struct platform_device bcma_pflash_dev; |
||
494 | +int bcma_pflash_init(struct bcma_drv_cc *cc); |
||
495 | +#else |
||
496 | +static inline int bcma_pflash_init(struct bcma_drv_cc *cc) |
||
497 | +{ |
||
498 | + bcma_err(cc->core->bus, "Parallel flash not supported\n"); |
||
499 | + return 0; |
||
500 | +} |
||
501 | +#endif /* CONFIG_BCMA_PFLASH */ |
||
502 | + |
||
503 | #ifdef CONFIG_BCMA_SFLASH |
||
504 | /* driver_chipcommon_sflash.c */ |
||
505 | int bcma_sflash_init(struct bcma_drv_cc *cc); |
||
506 | --- a/drivers/bcma/driver_gpio.c |
||
507 | +++ b/drivers/bcma/driver_gpio.c |
||
508 | @@ -229,6 +229,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c |
||
509 | case BCMA_CHIP_ID_BCM4707: |
||
510 | case BCMA_CHIP_ID_BCM5357: |
||
511 | case BCMA_CHIP_ID_BCM53572: |
||
512 | + case BCMA_CHIP_ID_BCM47094: |
||
513 | chip->ngpio = 32; |
||
514 | break; |
||
515 | default: |
||
516 | --- a/drivers/bcma/driver_mips.c |
||
517 | +++ b/drivers/bcma/driver_mips.c |
||
518 | @@ -14,8 +14,6 @@ |
||
519 | |||
520 | #include <linux/bcma/bcma.h> |
||
521 | |||
522 | -#include <linux/mtd/physmap.h> |
||
523 | -#include <linux/platform_device.h> |
||
524 | #include <linux/serial.h> |
||
525 | #include <linux/serial_core.h> |
||
526 | #include <linux/serial_reg.h> |
||
527 | @@ -29,26 +27,6 @@ enum bcma_boot_dev { |
||
528 | BCMA_BOOT_DEV_NAND, |
||
529 | }; |
||
530 | |||
531 | -static const char * const part_probes[] = { "bcm47xxpart", NULL }; |
||
532 | - |
||
533 | -static struct physmap_flash_data bcma_pflash_data = { |
||
534 | - .part_probe_types = part_probes, |
||
535 | -}; |
||
536 | - |
||
537 | -static struct resource bcma_pflash_resource = { |
||
538 | - .name = "bcma_pflash", |
||
539 | - .flags = IORESOURCE_MEM, |
||
540 | -}; |
||
541 | - |
||
542 | -struct platform_device bcma_pflash_dev = { |
||
543 | - .name = "physmap-flash", |
||
544 | - .dev = { |
||
545 | - .platform_data = &bcma_pflash_data, |
||
546 | - }, |
||
547 | - .resource = &bcma_pflash_resource, |
||
548 | - .num_resources = 1, |
||
549 | -}; |
||
550 | - |
||
551 | /* The 47162a0 hangs when reading MIPS DMP registers registers */ |
||
552 | static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) |
||
553 | { |
||
554 | @@ -269,48 +247,11 @@ static enum bcma_boot_dev bcma_boot_dev( |
||
555 | return BCMA_BOOT_DEV_SERIAL; |
||
556 | } |
||
557 | |||
558 | -static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) |
||
559 | +static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore) |
||
560 | { |
||
561 | struct bcma_bus *bus = mcore->core->bus; |
||
562 | - struct bcma_drv_cc *cc = &bus->drv_cc; |
||
563 | - struct bcma_pflash *pflash = &cc->pflash; |
||
564 | enum bcma_boot_dev boot_dev; |
||
565 | |||
566 | - switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { |
||
567 | - case BCMA_CC_FLASHT_STSER: |
||
568 | - case BCMA_CC_FLASHT_ATSER: |
||
569 | - bcma_debug(bus, "Found serial flash\n"); |
||
570 | - bcma_sflash_init(cc); |
||
571 | - break; |
||
572 | - case BCMA_CC_FLASHT_PARA: |
||
573 | - bcma_debug(bus, "Found parallel flash\n"); |
||
574 | - pflash->present = true; |
||
575 | - pflash->window = BCMA_SOC_FLASH2; |
||
576 | - pflash->window_size = BCMA_SOC_FLASH2_SZ; |
||
577 | - |
||
578 | - if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & |
||
579 | - BCMA_CC_FLASH_CFG_DS) == 0) |
||
580 | - pflash->buswidth = 1; |
||
581 | - else |
||
582 | - pflash->buswidth = 2; |
||
583 | - |
||
584 | - bcma_pflash_data.width = pflash->buswidth; |
||
585 | - bcma_pflash_resource.start = pflash->window; |
||
586 | - bcma_pflash_resource.end = pflash->window + pflash->window_size; |
||
587 | - |
||
588 | - break; |
||
589 | - default: |
||
590 | - bcma_err(bus, "Flash type not supported\n"); |
||
591 | - } |
||
592 | - |
||
593 | - if (cc->core->id.rev == 38 || |
||
594 | - bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { |
||
595 | - if (cc->capabilities & BCMA_CC_CAP_NFLASH) { |
||
596 | - bcma_debug(bus, "Found NAND flash\n"); |
||
597 | - bcma_nflash_init(cc); |
||
598 | - } |
||
599 | - } |
||
600 | - |
||
601 | /* Determine flash type this SoC boots from */ |
||
602 | boot_dev = bcma_boot_dev(bus); |
||
603 | switch (boot_dev) { |
||
604 | @@ -328,13 +269,10 @@ static void bcma_core_mips_flash_detect( |
||
605 | |||
606 | void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) |
||
607 | { |
||
608 | - struct bcma_bus *bus = mcore->core->bus; |
||
609 | - |
||
610 | if (mcore->early_setup_done) |
||
611 | return; |
||
612 | |||
613 | - bcma_chipco_serial_init(&bus->drv_cc); |
||
614 | - bcma_core_mips_flash_detect(mcore); |
||
615 | + bcma_core_mips_nvram_init(mcore); |
||
616 | |||
617 | mcore->early_setup_done = true; |
||
618 | } |
||
619 | --- a/drivers/bcma/host_pci.c |
||
620 | +++ b/drivers/bcma/host_pci.c |
||
621 | @@ -294,7 +294,7 @@ static const struct pci_device_id bcma_p |
||
622 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) }, |
||
623 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) }, |
||
624 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) }, |
||
625 | - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) }, |
||
626 | + { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) }, |
||
627 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) }, |
||
628 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) }, |
||
629 | { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) }, |
||
630 | --- a/drivers/bcma/Kconfig |
||
631 | +++ b/drivers/bcma/Kconfig |
||
632 | @@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS |
||
633 | |||
634 | If unsure, say N |
||
635 | |||
636 | +config BCMA_PFLASH |
||
637 | + bool |
||
638 | + depends on BCMA_DRIVER_MIPS |
||
639 | + default y |
||
640 | + |
||
641 | config BCMA_SFLASH |
||
642 | bool |
||
643 | depends on BCMA_DRIVER_MIPS |
||
644 | --- a/drivers/bcma/Makefile |
||
645 | +++ b/drivers/bcma/Makefile |
||
646 | @@ -1,6 +1,7 @@ |
||
647 | bcma-y += main.o scan.o core.o sprom.o |
||
648 | bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o |
||
649 | bcma-y += driver_chipcommon_b.o |
||
650 | +bcma-$(CONFIG_BCMA_PFLASH) += driver_chipcommon_pflash.o |
||
651 | bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o |
||
652 | bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o |
||
653 | bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o |
||
654 | --- /dev/null |
||
655 | +++ b/drivers/bcma/driver_chipcommon_pflash.c |
||
656 | @@ -0,0 +1,49 @@ |
||
657 | +/* |
||
658 | + * Broadcom specific AMBA |
||
659 | + * ChipCommon parallel flash |
||
660 | + * |
||
661 | + * Licensed under the GNU/GPL. See COPYING for details. |
||
662 | + */ |
||
663 | + |
||
664 | +#include "bcma_private.h" |
||
665 | + |
||
666 | +#include <linux/bcma/bcma.h> |
||
667 | +#include <linux/mtd/physmap.h> |
||
668 | +#include <linux/platform_device.h> |
||
669 | + |
||
670 | +static const char * const part_probes[] = { "bcm47xxpart", NULL }; |
||
671 | + |
||
672 | +static struct physmap_flash_data bcma_pflash_data = { |
||
673 | + .part_probe_types = part_probes, |
||
674 | +}; |
||
675 | + |
||
676 | +static struct resource bcma_pflash_resource = { |
||
677 | + .name = "bcma_pflash", |
||
678 | + .flags = IORESOURCE_MEM, |
||
679 | +}; |
||
680 | + |
||
681 | +struct platform_device bcma_pflash_dev = { |
||
682 | + .name = "physmap-flash", |
||
683 | + .dev = { |
||
684 | + .platform_data = &bcma_pflash_data, |
||
685 | + }, |
||
686 | + .resource = &bcma_pflash_resource, |
||
687 | + .num_resources = 1, |
||
688 | +}; |
||
689 | + |
||
690 | +int bcma_pflash_init(struct bcma_drv_cc *cc) |
||
691 | +{ |
||
692 | + struct bcma_pflash *pflash = &cc->pflash; |
||
693 | + |
||
694 | + pflash->present = true; |
||
695 | + |
||
696 | + if (!(bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS)) |
||
697 | + bcma_pflash_data.width = 1; |
||
698 | + else |
||
699 | + bcma_pflash_data.width = 2; |
||
700 | + |
||
701 | + bcma_pflash_resource.start = BCMA_SOC_FLASH2; |
||
702 | + bcma_pflash_resource.end = BCMA_SOC_FLASH2 + BCMA_SOC_FLASH2_SZ; |
||
703 | + |
||
704 | + return 0; |
||
705 | +} |
||
706 | --- a/drivers/bcma/main.c |
||
707 | +++ b/drivers/bcma/main.c |
||
708 | @@ -325,7 +325,7 @@ static int bcma_register_devices(struct |
||
709 | bcma_register_core(bus, core); |
||
710 | } |
||
711 | |||
712 | -#ifdef CONFIG_BCMA_DRIVER_MIPS |
||
713 | +#ifdef CONFIG_BCMA_PFLASH |
||
714 | if (bus->drv_cc.pflash.present) { |
||
715 | err = platform_device_register(&bcma_pflash_dev); |
||
716 | if (err) |