OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From: Ben Menchaca <ben.menchaca@qca.qualcomm.com> |
2 | Date: Fri, 7 Jun 2013 18:35:22 -0500 |
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3 | Subject: MIPS: r4k_cache: use more efficient cache blast |
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4 | |||
5 | Optimize the compiler output for larger cache blast cases that are |
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6 | common for DMA-based networking. |
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7 | |||
8 | Signed-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com> |
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9 | Signed-off-by: Felix Fietkau <nbd@nbd.name> |
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10 | --- |
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11 | --- a/arch/mips/include/asm/r4kcache.h |
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12 | +++ b/arch/mips/include/asm/r4kcache.h |
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13 | @@ -683,16 +683,48 @@ static inline void prot##extra##blast_## |
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14 | unsigned long end) \ |
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15 | { \ |
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16 | unsigned long lsize = cpu_##desc##_line_size(); \ |
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17 | + unsigned long lsize_2 = lsize * 2; \ |
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18 | + unsigned long lsize_3 = lsize * 3; \ |
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19 | + unsigned long lsize_4 = lsize * 4; \ |
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20 | + unsigned long lsize_5 = lsize * 5; \ |
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21 | + unsigned long lsize_6 = lsize * 6; \ |
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22 | + unsigned long lsize_7 = lsize * 7; \ |
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23 | + unsigned long lsize_8 = lsize * 8; \ |
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24 | unsigned long addr = start & ~(lsize - 1); \ |
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25 | - unsigned long aend = (end - 1) & ~(lsize - 1); \ |
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26 | + unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \ |
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27 | + int lines = (aend - addr) / lsize; \ |
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28 | \ |
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29 | __##pfx##flush_prologue \ |
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30 | \ |
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31 | - while (1) { \ |
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32 | + while (lines >= 8) { \ |
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33 | + prot##cache_op(hitop, addr); \ |
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34 | + prot##cache_op(hitop, addr + lsize); \ |
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35 | + prot##cache_op(hitop, addr + lsize_2); \ |
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36 | + prot##cache_op(hitop, addr + lsize_3); \ |
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37 | + prot##cache_op(hitop, addr + lsize_4); \ |
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38 | + prot##cache_op(hitop, addr + lsize_5); \ |
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39 | + prot##cache_op(hitop, addr + lsize_6); \ |
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40 | + prot##cache_op(hitop, addr + lsize_7); \ |
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41 | + addr += lsize_8; \ |
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42 | + lines -= 8; \ |
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43 | + } \ |
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44 | + \ |
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45 | + if (lines & 0x4) { \ |
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46 | + prot##cache_op(hitop, addr); \ |
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47 | + prot##cache_op(hitop, addr + lsize); \ |
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48 | + prot##cache_op(hitop, addr + lsize_2); \ |
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49 | + prot##cache_op(hitop, addr + lsize_3); \ |
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50 | + addr += lsize_4; \ |
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51 | + } \ |
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52 | + \ |
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53 | + if (lines & 0x2) { \ |
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54 | + prot##cache_op(hitop, addr); \ |
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55 | + prot##cache_op(hitop, addr + lsize); \ |
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56 | + addr += lsize_2; \ |
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57 | + } \ |
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58 | + \ |
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59 | + if (lines & 0x1) { \ |
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60 | prot##cache_op(hitop, addr); \ |
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61 | - if (addr == aend) \ |
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62 | - break; \ |
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63 | - addr += lsize; \ |
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64 | } \ |
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65 | \ |
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66 | __##pfx##flush_epilogue \ |