OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Marvell 88E61xx switch driver |
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3 | * |
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4 | * Copyright (c) 2014 Claudio Leite <leitec@staticky.com> |
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5 | * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com> |
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6 | * |
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7 | * Based on code (c) 2008 Felix Fietkau <nbd@nbd.name> |
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8 | * |
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9 | * This program is free software; you can redistribute it and/or modify it |
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10 | * under the terms of the GNU General Public License v2 as published by the |
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11 | * Free Software Foundation |
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12 | */ |
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13 | |||
14 | #ifndef __MVSW61XX_H |
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15 | #define __MVSW61XX_H |
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16 | |||
17 | #define MV_PORTS 7 |
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18 | #define MV_PORTS_MASK ((1 << MV_PORTS) - 1) |
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19 | |||
20 | #define MV_BASE 0x10 |
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21 | |||
22 | #define MV_SWITCHPORT_BASE 0x10 |
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23 | #define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n)) |
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24 | #define MV_SWITCHREGS (MV_BASE + 0xb) |
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25 | |||
26 | #define MV_VLANS 64 |
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27 | |||
28 | enum { |
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29 | MV_PORT_STATUS = 0x00, |
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30 | MV_PORT_PHYCTL = 0x01, |
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31 | MV_PORT_JAMCTL = 0x02, |
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32 | MV_PORT_IDENT = 0x03, |
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33 | MV_PORT_CONTROL = 0x04, |
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34 | MV_PORT_CONTROL1 = 0x05, |
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35 | MV_PORT_VLANMAP = 0x06, |
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36 | MV_PORT_VLANID = 0x07, |
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37 | MV_PORT_CONTROL2 = 0x08, |
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38 | MV_PORT_ASSOC = 0x0b, |
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39 | MV_PORT_RX_DISCARD_LOW = 0x10, |
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40 | MV_PORT_RX_DISCARD_HIGH = 0x11, |
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41 | MV_PORT_IN_FILTERED = 0x12, |
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42 | MV_PORT_OUT_ACCEPTED = 0x13, |
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43 | }; |
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44 | #define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type |
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45 | |||
46 | enum { |
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47 | MV_PORT_STATUS_FDX = (1 << 10), |
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48 | MV_PORT_STATUS_LINK = (1 << 11), |
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49 | }; |
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50 | |||
51 | enum { |
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52 | MV_PORT_STATUS_CMODE_100BASE_X = 0x8, |
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53 | MV_PORT_STATUS_CMODE_1000BASE_X = 0x9, |
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54 | MV_PORT_STATUS_CMODE_SGMII = 0xa, |
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55 | }; |
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56 | |||
57 | #define MV_PORT_STATUS_CMODE_MASK 0xf |
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58 | |||
59 | enum { |
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60 | MV_PORT_STATUS_SPEED_10 = 0x00, |
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61 | MV_PORT_STATUS_SPEED_100 = 0x01, |
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62 | MV_PORT_STATUS_SPEED_1000 = 0x02, |
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63 | }; |
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64 | #define MV_PORT_STATUS_SPEED_SHIFT 8 |
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65 | #define MV_PORT_STATUS_SPEED_MASK (3 << 8) |
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66 | |||
67 | enum { |
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68 | MV_PORTCTRL_DISABLED = (0 << 0), |
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69 | MV_PORTCTRL_BLOCKING = (1 << 0), |
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70 | MV_PORTCTRL_LEARNING = (2 << 0), |
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71 | MV_PORTCTRL_FORWARDING = (3 << 0), |
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72 | MV_PORTCTRL_VLANTUN = (1 << 7), |
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73 | MV_PORTCTRL_EGRESS = (1 << 12), |
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74 | }; |
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75 | |||
76 | #define MV_PHYCTL_FC_MASK (3 << 6) |
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77 | |||
78 | enum { |
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79 | MV_PHYCTL_FC_ENABLE = (3 << 6), |
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80 | MV_PHYCTL_FC_DISABLE = (1 << 6), |
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81 | }; |
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82 | |||
83 | enum { |
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84 | MV_8021Q_EGRESS_UNMODIFIED = 0x00, |
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85 | MV_8021Q_EGRESS_UNTAGGED = 0x01, |
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86 | MV_8021Q_EGRESS_TAGGED = 0x02, |
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87 | MV_8021Q_EGRESS_ADDTAG = 0x03, |
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88 | }; |
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89 | |||
90 | #define MV_8021Q_MODE_SHIFT 10 |
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91 | #define MV_8021Q_MODE_MASK (0x3 << MV_8021Q_MODE_SHIFT) |
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92 | |||
93 | enum { |
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94 | MV_8021Q_MODE_DISABLE = 0x00, |
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95 | MV_8021Q_MODE_FALLBACK = 0x01, |
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96 | MV_8021Q_MODE_CHECK = 0x02, |
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97 | MV_8021Q_MODE_SECURE = 0x03, |
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98 | }; |
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99 | |||
100 | enum { |
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101 | MV_8021Q_VLAN_ONLY = (1 << 15), |
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102 | }; |
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103 | |||
104 | #define MV_PORTASSOC_MONITOR (1 << 15) |
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105 | |||
106 | enum { |
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107 | MV_SWITCH_ATU_FID0 = 0x01, |
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108 | MV_SWITCH_ATU_FID1 = 0x02, |
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109 | MV_SWITCH_ATU_SID = 0x03, |
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110 | MV_SWITCH_CTRL = 0x04, |
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111 | MV_SWITCH_ATU_CTRL = 0x0a, |
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112 | MV_SWITCH_ATU_OP = 0x0b, |
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113 | MV_SWITCH_ATU_DATA = 0x0c, |
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114 | MV_SWITCH_ATU_MAC0 = 0x0d, |
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115 | MV_SWITCH_ATU_MAC1 = 0x0e, |
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116 | MV_SWITCH_ATU_MAC2 = 0x0f, |
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117 | MV_SWITCH_GLOBAL = 0x1b, |
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118 | MV_SWITCH_GLOBAL2 = 0x1c, |
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119 | }; |
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120 | #define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type |
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121 | |||
122 | enum { |
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123 | MV_SWITCHCTL_EEIE = (1 << 0), |
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124 | MV_SWITCHCTL_PHYIE = (1 << 1), |
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125 | MV_SWITCHCTL_ATUDONE = (1 << 2), |
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126 | MV_SWITCHCTL_ATUIE = (1 << 3), |
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127 | MV_SWITCHCTL_CTRMODE = (1 << 8), |
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128 | MV_SWITCHCTL_RELOAD = (1 << 9), |
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129 | MV_SWITCHCTL_MSIZE = (1 << 10), |
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130 | MV_SWITCHCTL_DROP = (1 << 13), |
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131 | }; |
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132 | |||
133 | enum { |
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134 | #define MV_ATUCTL_AGETIME_MIN 16 |
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135 | #define MV_ATUCTL_AGETIME_MAX 4080 |
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136 | #define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4) |
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137 | MV_ATUCTL_ATU_256 = (0 << 12), |
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138 | MV_ATUCTL_ATU_512 = (1 << 12), |
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139 | MV_ATUCTL_ATU_1K = (2 << 12), |
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140 | MV_ATUCTL_ATUMASK = (3 << 12), |
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141 | MV_ATUCTL_NO_LEARN = (1 << 14), |
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142 | MV_ATUCTL_RESET = (1 << 15), |
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143 | }; |
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144 | |||
145 | enum { |
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146 | #define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f) |
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147 | MV_ATUOP_NOOP = (0 << 12), |
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148 | MV_ATUOP_FLUSH_ALL = (1 << 12), |
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149 | MV_ATUOP_FLUSH_U = (2 << 12), |
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150 | MV_ATUOP_LOAD_DB = (3 << 12), |
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151 | MV_ATUOP_GET_NEXT = (4 << 12), |
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152 | MV_ATUOP_FLUSH_DB = (5 << 12), |
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153 | MV_ATUOP_FLUSH_DB_UU = (6 << 12), |
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154 | MV_ATUOP_INPROGRESS = (1 << 15), |
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155 | }; |
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156 | |||
157 | enum { |
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158 | MV_GLOBAL_STATUS = 0x00, |
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159 | MV_GLOBAL_ATU_FID = 0x01, |
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160 | MV_GLOBAL_VTU_FID = 0x02, |
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161 | MV_GLOBAL_VTU_SID = 0x03, |
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162 | MV_GLOBAL_CONTROL = 0x04, |
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163 | MV_GLOBAL_VTU_OP = 0x05, |
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164 | MV_GLOBAL_VTU_VID = 0x06, |
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165 | MV_GLOBAL_VTU_DATA1 = 0x07, |
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166 | MV_GLOBAL_VTU_DATA2 = 0x08, |
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167 | MV_GLOBAL_VTU_DATA3 = 0x09, |
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168 | MV_GLOBAL_MONITOR_CTRL = 0x1a, |
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169 | MV_GLOBAL_CONTROL2 = 0x1c, |
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170 | }; |
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171 | #define MV_GLOBALREG(_type) MV_SWITCH_GLOBAL, MV_GLOBAL_##_type |
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172 | |||
173 | enum { |
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174 | MV_GLOBAL2_SMI_OP = 0x18, |
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175 | MV_GLOBAL2_SMI_DATA = 0x19, |
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176 | MV_GLOBAL2_SDET_POLARITY = 0x1d, |
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177 | }; |
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178 | #define MV_GLOBAL2REG(_type) MV_SWITCH_GLOBAL2, MV_GLOBAL2_##_type |
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179 | |||
180 | enum { |
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181 | MV_VTU_VID_VALID = (1 << 12), |
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182 | }; |
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183 | |||
184 | enum { |
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185 | MV_VTUOP_PURGE = (1 << 12), |
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186 | MV_VTUOP_LOAD = (3 << 12), |
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187 | MV_VTUOP_INPROGRESS = (1 << 15), |
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188 | MV_VTUOP_STULOAD = (5 << 12), |
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189 | MV_VTUOP_VTU_GET_NEXT = (4 << 12), |
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190 | MV_VTUOP_STU_GET_NEXT = (6 << 12), |
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191 | MV_VTUOP_GET_VIOLATION = (7 << 12), |
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192 | }; |
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193 | |||
194 | enum { |
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195 | MV_CONTROL_RESET = (1 << 15), |
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196 | MV_CONTROL_PPU_ENABLE = (1 << 14), |
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197 | }; |
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198 | |||
199 | enum { |
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200 | MV_VTUCTL_EGRESS_UNMODIFIED = (0 << 0), |
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201 | MV_VTUCTL_EGRESS_UNTAGGED = (1 << 0), |
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202 | MV_VTUCTL_EGRESS_TAGGED = (2 << 0), |
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203 | MV_VTUCTL_DISCARD = (3 << 0), |
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204 | }; |
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205 | |||
206 | enum { |
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207 | MV_STUCTL_STATE_DISABLED = (0 << 0), |
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208 | MV_STUCTL_STATE_BLOCKING = (1 << 0), |
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209 | MV_STUCTL_STATE_LEARNING = (2 << 0), |
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210 | MV_STUCTL_STATE_FORWARDING = (3 << 0), |
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211 | }; |
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212 | |||
213 | enum { |
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214 | MV_INDIRECT_REG_CMD = 0, |
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215 | MV_INDIRECT_REG_DATA = 1, |
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216 | }; |
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217 | |||
218 | enum { |
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219 | MV_INDIRECT_INPROGRESS = 0x8000, |
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220 | MV_INDIRECT_WRITE = 0x9400, |
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221 | MV_INDIRECT_READ = 0x9800, |
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222 | }; |
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223 | #define MV_INDIRECT_ADDR_S 5 |
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224 | |||
225 | #define MV_IDENT_MASK 0xfff0 |
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226 | |||
227 | #define MV_IDENT_VALUE_6171 0x1710 |
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228 | #define MV_IDENT_STR_6171 "MV88E6171" |
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229 | |||
230 | #define MV_IDENT_VALUE_6172 0x1720 |
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231 | #define MV_IDENT_STR_6172 "MV88E6172" |
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232 | |||
233 | #define MV_IDENT_VALUE_6176 0x1760 |
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234 | #define MV_IDENT_STR_6176 "MV88E6176" |
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235 | |||
236 | #define MV_IDENT_VALUE_6352 0x3520 |
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237 | #define MV_IDENT_STR_6352 "MV88E6352" |
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238 | |||
239 | #define MV_PVID_MASK 0x0fff |
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240 | |||
241 | #define MV_FDB_HI_MASK 0x00ff |
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242 | #define MV_FDB_LO_MASK 0xf000 |
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243 | #define MV_FDB_HI_SHIFT 4 |
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244 | #define MV_FDB_LO_SHIFT 12 |
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245 | |||
246 | #define MV_MIRROR_RX_DEST_MASK 0xf000 |
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247 | #define MV_MIRROR_TX_DEST_MASK 0x0f00 |
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248 | #define MV_MIRROR_RX_DEST_SHIFT 12 |
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249 | #define MV_MIRROR_TX_DEST_SHIFT 8 |
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250 | |||
251 | #define MV_MIRROR_RX_SRC_SHIFT 4 |
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252 | #define MV_MIRROR_RX_SRC_MASK (1 << MV_MIRROR_RX_SRC_SHIFT) |
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253 | #define MV_MIRROR_TX_SRC_SHIFT 5 |
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254 | #define MV_MIRROR_TX_SRC_MASK (1 << MV_MIRROR_TX_SRC_SHIFT) |
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255 | |||
256 | /* Marvell Specific PHY register */ |
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257 | #define MII_MV_SPEC_CTRL 16 |
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258 | enum { |
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259 | MV_SPEC_MDI_CROSS_AUTO = (0x6 << 4), |
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260 | MV_SPEC_ENERGY_DETECT = (0x3 << 8), |
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261 | MV_SPEC_DOWNSHIFT_COUNTER = (0x3 << 12), |
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262 | }; |
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263 | |||
264 | #define MII_MV_PAGE 22 |
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265 | |||
266 | #define MV_REG_FIBER_SERDES 0xf |
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267 | #define MV_PAGE_FIBER_SERDES 0x1 |
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268 | |||
269 | struct mvsw61xx_state { |
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270 | struct switch_dev dev; |
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271 | struct mii_bus *bus; |
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272 | int base_addr; |
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273 | u16 model; |
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274 | |||
275 | bool registered; |
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276 | bool is_indirect; |
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277 | |||
278 | int cpu_port0; |
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279 | int cpu_port1; |
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280 | |||
281 | int vlan_enabled; |
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282 | struct port_state { |
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283 | u16 fdb; |
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284 | u16 pvid; |
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285 | u16 mask; |
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286 | u8 qmode; |
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287 | } ports[MV_PORTS]; |
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288 | |||
289 | struct vlan_state { |
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290 | bool port_based; |
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291 | |||
292 | u16 mask; |
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293 | u16 vid; |
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294 | u32 port_mode; |
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295 | u32 port_sstate; |
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296 | } vlans[MV_VLANS]; |
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297 | |||
298 | /* mirroring */ |
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299 | bool mirror_rx; |
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300 | bool mirror_tx; |
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301 | int source_port; |
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302 | int monitor_port; |
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303 | |||
304 | char buf[128]; |
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305 | }; |
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306 | |||
307 | #define get_state(_dev) container_of((_dev), struct mvsw61xx_state, dev) |
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308 | |||
309 | #endif |