OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-cns3xxx/pcie.c |
2 | +++ b/arch/arm/mach-cns3xxx/pcie.c |
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3 | @@ -86,6 +86,79 @@ static void __iomem *cns3xxx_pci_map_bus |
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3 | office | 4 | return base + (where & 0xffc) + (devfn << 12); |
1 | office | 5 | } |
6 | |||
7 | +static inline int check_master_abort(struct pci_bus *bus, unsigned int devfn, int where) |
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8 | +{ |
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9 | + struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); |
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10 | + |
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11 | + /* check PCI-compatible status register after access */ |
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12 | + if (cnspci->linked) { |
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13 | + void __iomem *host_base; |
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14 | + u32 sreg, ereg; |
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15 | + |
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16 | + host_base = (void __iomem *) cnspci->cfg_bases[CNS3XXX_HOST_TYPE].virtual; |
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17 | + sreg = __raw_readw(host_base + 0x6) & 0xF900; |
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18 | + ereg = __raw_readl(host_base + 0x104); // Uncorrectable Error Status Reg |
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19 | + |
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20 | + if (sreg | ereg) { |
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21 | + /* SREG: |
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22 | + * BIT15 - Detected Parity Error |
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23 | + * BIT14 - Signaled System Error |
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24 | + * BIT13 - Received Master Abort |
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25 | + * BIT12 - Received Target Abort |
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26 | + * BIT11 - Signaled Target Abort |
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27 | + * BIT08 - Master Data Parity Error |
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28 | + * |
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29 | + * EREG: |
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30 | + * BIT20 - Unsupported Request |
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31 | + * BIT19 - ECRC |
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32 | + * BIT18 - Malformed TLP |
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33 | + * BIT17 - Receiver Overflow |
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34 | + * BIT16 - Unexpected Completion |
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35 | + * BIT15 - Completer Abort |
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36 | + * BIT14 - Completion Timeout |
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37 | + * BIT13 - Flow Control Protocol Error |
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38 | + * BIT12 - Poisoned TLP |
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39 | + * BIT04 - Data Link Protocol Error |
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40 | + * |
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41 | + * TODO: see Documentation/pci-error-recovery.txt |
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42 | + * implement error_detected handler |
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43 | + */ |
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44 | +/* |
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45 | + printk("pci error: %04d:%02x:%02x.%02x sreg=0x%04x ereg=0x%08x", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), sreg, ereg); |
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46 | + if (sreg & BIT(15)) printk(" <PERR"); |
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47 | + if (sreg & BIT(14)) printk(" >SERR"); |
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48 | + if (sreg & BIT(13)) printk(" <MABRT"); |
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49 | + if (sreg & BIT(12)) printk(" <TABRT"); |
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50 | + if (sreg & BIT(11)) printk(" >TABRT"); |
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51 | + if (sreg & BIT( 8)) printk(" MPERR"); |
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52 | + |
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53 | + if (ereg & BIT(20)) printk(" Unsup"); |
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54 | + if (ereg & BIT(19)) printk(" ECRC"); |
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55 | + if (ereg & BIT(18)) printk(" MTLP"); |
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56 | + if (ereg & BIT(17)) printk(" OFLOW"); |
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57 | + if (ereg & BIT(16)) printk(" Unex"); |
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58 | + if (ereg & BIT(15)) printk(" ABRT"); |
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59 | + if (ereg & BIT(14)) printk(" COMPTO"); |
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60 | + if (ereg & BIT(13)) printk(" FLOW"); |
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61 | + if (ereg & BIT(12)) printk(" PTLP"); |
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62 | + if (ereg & BIT( 4)) printk(" DLINK"); |
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63 | + printk("\n"); |
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64 | +*/ |
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65 | + pr_debug("%s failed port%d sreg=0x%04x\n", __func__, |
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66 | + pci_domain_nr(bus), sreg); |
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67 | + |
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68 | + /* make sure the status bits are reset */ |
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69 | + __raw_writew(sreg, host_base + 6); |
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70 | + __raw_writel(ereg, host_base + 0x104); |
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71 | + return 1; |
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72 | + } |
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73 | + } |
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74 | + else |
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75 | + return 1; |
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76 | + |
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77 | + return 0; |
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78 | +} |
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79 | + |
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80 | static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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81 | int where, int size, u32 *val) |
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82 | { |
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83 | @@ -95,6 +168,11 @@ static int cns3xxx_pci_read_config(struc |
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84 | |||
3 | office | 85 | ret = pci_generic_config_read32(bus, devfn, where, size, val); |
1 | office | 86 | |
87 | + if (check_master_abort(bus, devfn, where)) { |
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88 | + printk(KERN_ERR "pci error: %04d:%02x:%02x.%02x %02x(%d)= master_abort on read\n", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); |
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89 | + return PCIBIOS_DEVICE_NOT_FOUND; |
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90 | + } |
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91 | + |
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92 | if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn && |
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93 | (where & 0xffc) == PCI_CLASS_REVISION) |
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94 | /* |
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95 | @@ -257,8 +335,14 @@ static void __init cns3xxx_pcie_hw_init( |
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96 | static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, |
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97 | struct pt_regs *regs) |
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98 | { |
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99 | +#if 0 |
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100 | +/* R14_ABORT = PC+4 for XSCALE but not ARM11MPCORE |
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101 | + * ignore imprecise aborts and use PCI-compatible Status register to |
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102 | + * determine errors instead |
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103 | + */ |
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104 | if (fsr & (1 << 10)) |
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105 | regs->ARM_pc += 4; |
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106 | +#endif |
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107 | return 0; |
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108 | } |
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109 |