OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/arm/mach-cns3xxx/Kconfig |
2 | +++ b/arch/arm/mach-cns3xxx/Kconfig |
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3 | @@ -6,6 +6,7 @@ menuconfig ARCH_CNS3XXX |
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4 | select HAVE_ARM_SCU if SMP |
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5 | select HAVE_ARM_TWD |
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6 | select HAVE_SMP |
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7 | + select FIQ |
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8 | help |
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9 | Support for Cavium Networks CNS3XXX platform. |
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10 | |||
11 | --- a/arch/arm/mach-cns3xxx/Makefile |
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12 | +++ b/arch/arm/mach-cns3xxx/Makefile |
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13 | @@ -6,5 +6,5 @@ cns3xxx-y += core.o pm.o |
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14 | cns3xxx-$(CONFIG_ATAGS) += devices.o |
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15 | cns3xxx-$(CONFIG_PCI) += pcie.o |
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16 | cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o |
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17 | -cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o |
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18 | +cns3xxx-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o |
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19 | cns3xxx-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
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20 | --- a/arch/arm/mach-cns3xxx/cns3xxx.h |
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21 | +++ b/arch/arm/mach-cns3xxx/cns3xxx.h |
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22 | @@ -261,6 +261,7 @@ |
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23 | #define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) |
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24 | #define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) |
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25 | |||
26 | +#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4) |
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27 | /* |
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28 | * Power management and clock control |
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29 | */ |
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30 | --- a/arch/arm/mm/Kconfig |
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31 | +++ b/arch/arm/mm/Kconfig |
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3 | office | 32 | @@ -882,7 +882,7 @@ config VDSO |
1 | office | 33 | |
34 | config DMA_CACHE_RWFO |
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35 | bool "Enable read/write for ownership DMA cache maintenance" |
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36 | - depends on CPU_V6K && SMP |
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37 | + depends on CPU_V6K && SMP && !ARCH_CNS3XXX |
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38 | default y |
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39 | help |
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40 | The Snoop Control Unit on ARM11MPCore does not detect the |