OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Sun, 3 Jul 2011 15:00:38 +0200 |
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4 | Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present |
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5 | |||
6 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
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7 | --- |
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8 | arch/mips/bcm63xx/dev-flash.c | 35 +++++++++++++++++++- |
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9 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 + |
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10 | 2 files changed, 33 insertions(+), 2 deletions(-) |
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11 | |||
12 | --- a/arch/mips/bcm63xx/dev-flash.c |
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13 | +++ b/arch/mips/bcm63xx/dev-flash.c |
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14 | @@ -17,6 +17,9 @@ |
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15 | #include <linux/mtd/partitions.h> |
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16 | #include <linux/mtd/physmap.h> |
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17 | #include <linux/mtd/spi-nor.h> |
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18 | +#include <linux/of.h> |
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19 | +#include <linux/spi/spi.h> |
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20 | +#include <linux/spi/flash.h> |
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21 | |||
22 | #include <bcm63xx_cpu.h> |
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23 | #include <bcm63xx_dev_flash.h> |
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24 | @@ -66,6 +69,41 @@ void __init bcm63xx_flash_force_phys_bas |
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25 | mtd_resources[0].end = end; |
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26 | } |
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27 | |||
28 | +static struct spi_board_info bcm63xx_spi_flash_info[] = { |
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29 | + { |
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30 | + .bus_num = 0, |
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31 | + .chip_select = 0, |
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32 | + .mode = 0, |
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33 | + .max_speed_hz = 781000, |
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34 | + .modalias = "m25p80", |
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35 | + }, |
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36 | +}; |
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37 | + |
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38 | +static void bcm63xx_of_update_spi_flash_speed(struct device_node *np, |
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39 | + unsigned int new_hz) |
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40 | +{ |
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41 | + struct property *max_hz; |
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42 | + __be32 *hz; |
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43 | + |
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44 | + max_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL); |
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45 | + if (!max_hz) |
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46 | + return; |
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47 | + |
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48 | + max_hz->name = kstrdup("spi-max-frequency", GFP_KERNEL); |
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49 | + if (!max_hz->name) { |
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50 | + kfree(max_hz); |
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51 | + return; |
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52 | + } |
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53 | + |
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54 | + max_hz->value = max_hz + 1; |
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55 | + max_hz->length = sizeof(*hz); |
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56 | + |
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57 | + hz = max_hz->value; |
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58 | + *hz = cpu_to_be32(new_hz); |
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59 | + |
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60 | + of_update_property(np, max_hz); |
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61 | +} |
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62 | + |
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63 | static int __init bcm63xx_detect_flash_type(void) |
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64 | { |
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65 | u32 val; |
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66 | @@ -73,9 +111,15 @@ static int __init bcm63xx_detect_flash_t |
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67 | switch (bcm63xx_get_cpu_id()) { |
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68 | case BCM6318_CPU_ID: |
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69 | /* only support serial flash */ |
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70 | + bcm63xx_spi_flash_info[0].max_speed_hz = 62500000; |
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71 | return BCM63XX_FLASH_TYPE_SERIAL; |
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72 | case BCM6328_CPU_ID: |
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73 | val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); |
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74 | + if (val & STRAPBUS_6328_HSSPI_CLK_FAST) |
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75 | + bcm63xx_spi_flash_info[0].max_speed_hz = 33333334; |
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76 | + else |
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77 | + bcm63xx_spi_flash_info[0].max_speed_hz = 16666667; |
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78 | + |
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79 | if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) |
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80 | return BCM63XX_FLASH_TYPE_SERIAL; |
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81 | else |
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82 | @@ -94,12 +138,20 @@ static int __init bcm63xx_detect_flash_t |
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83 | return BCM63XX_FLASH_TYPE_SERIAL; |
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84 | case BCM6362_CPU_ID: |
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85 | val = bcm_misc_readl(MISC_STRAPBUS_6362_REG); |
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86 | + if (val & STRAPBUS_6362_HSSPI_CLK_FAST) |
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87 | + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; |
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88 | + else |
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89 | + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; |
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90 | + |
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91 | if (val & STRAPBUS_6362_BOOT_SEL_SERIAL) |
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92 | return BCM63XX_FLASH_TYPE_SERIAL; |
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93 | else |
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94 | return BCM63XX_FLASH_TYPE_NAND; |
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95 | case BCM6368_CPU_ID: |
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96 | val = bcm_gpio_readl(GPIO_STRAPBUS_REG); |
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97 | + if (val & STRAPBUS_6368_SPI_CLK_FAST) |
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98 | + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; |
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99 | + |
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100 | switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { |
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101 | case STRAPBUS_6368_BOOT_SEL_NAND: |
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102 | return BCM63XX_FLASH_TYPE_NAND; |
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103 | @@ -110,6 +162,11 @@ static int __init bcm63xx_detect_flash_t |
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104 | } |
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105 | case BCM63268_CPU_ID: |
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106 | val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); |
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107 | + if (val & STRAPBUS_63268_HSSPI_CLK_FAST) |
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108 | + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000; |
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109 | + else |
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110 | + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000; |
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111 | + |
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112 | if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) |
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113 | return BCM63XX_FLASH_TYPE_SERIAL; |
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114 | else |
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115 | @@ -176,6 +233,7 @@ void __init bcm63xx_flash_detect(void) |
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116 | |||
117 | int __init bcm63xx_flash_register(void) |
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118 | { |
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119 | + struct device_node *np; |
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120 | u32 val; |
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121 | |||
122 | switch (flash_type) { |
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123 | @@ -195,8 +253,14 @@ int __init bcm63xx_flash_register(void) |
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124 | |||
125 | return platform_device_register(&mtd_dev); |
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126 | case BCM63XX_FLASH_TYPE_SERIAL: |
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127 | - pr_warn("unsupported serial flash detected\n"); |
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128 | - return -ENODEV; |
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129 | + np = of_find_compatible_node(NULL, NULL, "jedec,spi-nor"); |
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130 | + if (np) { |
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131 | + bcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz); |
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132 | + of_node_put(np); |
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133 | + return 0; |
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134 | + } else { |
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135 | + return -ENODEV; |
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136 | + } |
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137 | case BCM63XX_FLASH_TYPE_NAND: |
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138 | pr_warn("unsupported NAND flash detected\n"); |
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139 | return -ENODEV; |
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140 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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141 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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142 | @@ -708,6 +708,7 @@ |
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143 | #define GPIO_STRAPBUS_REG 0x40 |
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144 | #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) |
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145 | #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) |
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146 | +#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6) |
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147 | #define STRAPBUS_6368_BOOT_SEL_MASK 0x3 |
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148 | #define STRAPBUS_6368_BOOT_SEL_NAND 0 |
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149 | #define STRAPBUS_6368_BOOT_SEL_SERIAL 1 |
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150 | @@ -1564,6 +1565,7 @@ |
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151 | #define IDDQ_CTRL_63268_USBH (1 << 4) |
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152 | |||
153 | #define MISC_STRAPBUS_6328_REG 0x240 |
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154 | +#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4) |
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155 | #define STRAPBUS_6328_FCVO_SHIFT 7 |
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156 | #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) |
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157 | #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) |