OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/bcm63xx/usb-common.c |
2 | +++ b/arch/mips/bcm63xx/usb-common.c |
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3 | @@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) |
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4 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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5 | reg |= USBH_PRIV_SETUP_IOC_MASK; |
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6 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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7 | + } else if (BCMCPU_IS_6318()) { |
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8 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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9 | + reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; |
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10 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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11 | + |
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12 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); |
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13 | + reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; |
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14 | + reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; |
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15 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); |
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16 | + |
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17 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); |
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18 | + reg |= USBH_PRIV_SETUP_IOC_MASK; |
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19 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); |
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20 | + |
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21 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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22 | + reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; |
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23 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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24 | + |
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25 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); |
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26 | + reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; |
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27 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); |
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28 | } |
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29 | |||
30 | spin_unlock_irqrestore(&usb_priv_reg_lock, flags); |
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31 | @@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) |
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32 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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33 | reg |= USBH_PRIV_SETUP_IOC_MASK; |
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34 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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35 | + } else if (BCMCPU_IS_6318()) { |
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36 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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37 | + reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; |
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38 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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39 | + |
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40 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); |
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41 | + reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; |
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42 | + reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; |
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43 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG); |
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44 | + |
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45 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG); |
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46 | + reg |= USBH_PRIV_SETUP_IOC_MASK; |
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47 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); |
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48 | + |
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49 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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50 | + reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; |
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51 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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52 | + |
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53 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); |
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54 | + reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL; |
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55 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG); |
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56 | } |
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57 | |||
58 | spin_unlock_irqrestore(&usb_priv_reg_lock, flags); |
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59 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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60 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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61 | @@ -681,6 +681,12 @@ |
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62 | #define GPIO_MODE_6368_SPI_SSN4 (1 << 30) |
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63 | #define GPIO_MODE_6368_SPI_SSN5 (1 << 31) |
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64 | |||
65 | +#define GPIO_PINMUX_SEL0_6318 0x1c |
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66 | +#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26 |
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67 | +#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) |
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68 | +#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) |
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69 | +#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) |
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70 | +#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT) |
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71 | |||
72 | #define GPIO_PINMUX_OTHR_REG 0x24 |
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73 | #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12 |
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74 | @@ -999,6 +1005,7 @@ |
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75 | |||
76 | #define USBH_PRIV_SWAP_6358_REG 0x0 |
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77 | #define USBH_PRIV_SWAP_6368_REG 0x1c |
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78 | +#define USBH_PRIV_SWAP_6318_REG 0x0c |
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79 | |||
80 | #define USBH_PRIV_SWAP_USBD_SHIFT 6 |
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81 | #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT) |
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82 | @@ -1024,6 +1031,13 @@ |
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83 | #define USBH_PRIV_SETUP_IOC_SHIFT 4 |
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84 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) |
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85 | |||
86 | +#define USBH_PRIV_SETUP_6318_REG 0x00 |
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87 | +#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 |
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88 | +#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) |
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89 | +#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) |
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90 | +#define USBH_PRIV_SIM_CTRL_6318_REG 0x20 |
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91 | +#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) |
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92 | + |
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93 | |||
94 | /************************************************************************* |
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95 | * _REG relative to RSET_USBD |
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96 | --- a/arch/mips/bcm63xx/boards/board_common.c |
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97 | +++ b/arch/mips/bcm63xx/boards/board_common.c |
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3 | office | 98 | @@ -126,6 +126,15 @@ void __init board_early_setup(const stru |
1 | office | 99 | } |
100 | |||
101 | bcm_gpio_writel(val, GPIO_MODE_REG); |
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102 | + |
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103 | +#if IS_ENABLED(CONFIG_USB) |
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104 | + if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) { |
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105 | + val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318); |
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106 | + val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK; |
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107 | + val |= GPIO_PINMUX_SEL0_GPIO13_PWRON; |
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108 | + bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318); |
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109 | + } |
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110 | +#endif |
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111 | } |
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112 | |||
113 | |||
114 | --- a/arch/mips/bcm63xx/Kconfig |
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115 | +++ b/arch/mips/bcm63xx/Kconfig |
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116 | @@ -22,6 +22,8 @@ config BCM63XX_CPU_6318 |
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117 | bool "support 6318 CPU" |
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118 | select SYS_HAS_CPU_BMIPS32_3300 |
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119 | select HW_HAS_PCI |
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120 | + select BCM63XX_OHCI |
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121 | + select BCM63XX_EHCI |
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122 | |||
123 | config BCM63XX_CPU_6328 |
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124 | bool "support 6328 CPU" |