OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 8 Dec 2013 14:17:50 +0100 |
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4 | Subject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals |
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5 | |||
6 | --- |
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7 | arch/mips/bcm63xx/reset.c | 39 ++++++++++++++-------- |
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8 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h | 2 ++ |
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9 | arch/mips/pci/pci-bcm63xx.c | 7 ++++ |
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10 | 3 files changed, 34 insertions(+), 14 deletions(-) |
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11 | |||
12 | --- a/arch/mips/bcm63xx/reset.c |
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13 | +++ b/arch/mips/bcm63xx/reset.c |
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14 | @@ -28,7 +28,9 @@ |
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15 | [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \ |
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16 | [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \ |
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17 | [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ |
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18 | - [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, |
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19 | + [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, \ |
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20 | + [BCM63XX_RESET_PCIE_CORE] = BCM## __cpu ##_RESET_PCIE_CORE, \ |
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21 | + [BCM63XX_RESET_PCIE_HARD] = BCM## __cpu ##_RESET_PCIE_HARD, |
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22 | |||
23 | #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK |
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24 | #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK |
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25 | @@ -42,6 +44,8 @@ |
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26 | #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK |
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27 | #define BCM3368_RESET_PCIE 0 |
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28 | #define BCM3368_RESET_PCIE_EXT 0 |
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29 | +#define BCM3368_RESET_PCIE_CORE 0 |
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30 | +#define BCM3368_RESET_PCIE_HARD 0 |
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31 | |||
32 | |||
33 | #define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK |
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34 | @@ -54,11 +58,10 @@ |
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35 | #define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK |
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36 | #define BCM6318_RESET_PCM 0 |
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37 | #define BCM6318_RESET_MPI 0 |
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38 | -#define BCM6318_RESET_PCIE \ |
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39 | - (SOFTRESET_6318_PCIE_MASK | \ |
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40 | - SOFTRESET_6318_PCIE_CORE_MASK | \ |
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41 | - SOFTRESET_6318_PCIE_HARD_MASK) |
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42 | +#define BCM6318_RESET_PCIE SOFTRESET_6318_PCIE_MASK |
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43 | #define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK |
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44 | +#define BCM6318_RESET_PCIE_CORE SOFTRESET_6318_PCIE_CORE_MASK |
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45 | +#define BCM6318_RESET_PCIE_HARD SOFTRESET_6318_PCIE_HARD_MASK |
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46 | |||
47 | #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK |
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48 | #define BCM6328_RESET_ENET 0 |
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49 | @@ -70,11 +73,10 @@ |
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50 | #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK |
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51 | #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK |
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52 | #define BCM6328_RESET_MPI 0 |
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53 | -#define BCM6328_RESET_PCIE \ |
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54 | - (SOFTRESET_6328_PCIE_MASK | \ |
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55 | - SOFTRESET_6328_PCIE_CORE_MASK | \ |
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56 | - SOFTRESET_6328_PCIE_HARD_MASK) |
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57 | +#define BCM6328_RESET_PCIE SOFTRESET_6328_PCIE_MASK |
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58 | #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK |
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59 | +#define BCM6328_RESET_PCIE_CORE SOFTRESET_6328_PCIE_CORE_MASK |
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60 | +#define BCM6328_RESET_PCIE_HARD SOFTRESET_6328_PCIE_HARD_MASK |
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61 | |||
62 | #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK |
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63 | #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK |
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64 | @@ -88,6 +90,8 @@ |
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65 | #define BCM6338_RESET_MPI 0 |
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66 | #define BCM6338_RESET_PCIE 0 |
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67 | #define BCM6338_RESET_PCIE_EXT 0 |
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68 | +#define BCM6338_RESET_PCIE_CORE 0 |
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69 | +#define BCM6338_RESET_PCIE_HARD 0 |
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70 | |||
71 | #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK |
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72 | #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK |
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73 | @@ -101,6 +105,8 @@ |
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74 | #define BCM6348_RESET_MPI 0 |
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75 | #define BCM6348_RESET_PCIE 0 |
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76 | #define BCM6348_RESET_PCIE_EXT 0 |
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77 | +#define BCM6348_RESET_PCIE_CORE 0 |
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78 | +#define BCM6348_RESET_PCIE_HARD 0 |
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79 | |||
80 | #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK |
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81 | #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK |
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82 | @@ -114,6 +120,8 @@ |
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83 | #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK |
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84 | #define BCM6358_RESET_PCIE 0 |
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85 | #define BCM6358_RESET_PCIE_EXT 0 |
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86 | +#define BCM6358_RESET_PCIE_CORE 0 |
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87 | +#define BCM6358_RESET_PCIE_HARD 0 |
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88 | |||
89 | #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK |
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90 | #define BCM6362_RESET_ENET 0 |
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91 | @@ -125,9 +133,10 @@ |
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92 | #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK |
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93 | #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK |
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94 | #define BCM6362_RESET_MPI 0 |
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95 | -#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \ |
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96 | - SOFTRESET_6362_PCIE_CORE_MASK) |
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97 | +#define BCM6362_RESET_PCIE SOFTRESET_6362_PCIE_MASK |
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98 | #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK |
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99 | +#define BCM6362_RESET_PCIE_CORE SOFTRESET_6362_PCIE_CORE_MASK |
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100 | +#define BCM6362_RESET_PCIE_HARD 0 |
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101 | |||
102 | #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK |
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103 | #define BCM6368_RESET_ENET 0 |
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104 | @@ -141,6 +150,8 @@ |
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105 | #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK |
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106 | #define BCM6368_RESET_PCIE 0 |
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107 | #define BCM6368_RESET_PCIE_EXT 0 |
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108 | +#define BCM6368_RESET_PCIE_CORE 0 |
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109 | +#define BCM6368_RESET_PCIE_HARD 0 |
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110 | |||
111 | #define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK |
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112 | #define BCM63268_RESET_ENET 0 |
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113 | @@ -152,10 +163,10 @@ |
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114 | #define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK |
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115 | #define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK |
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116 | #define BCM63268_RESET_MPI 0 |
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117 | -#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ |
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118 | - SOFTRESET_63268_PCIE_CORE_MASK | \ |
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119 | - SOFTRESET_63268_PCIE_HARD_MASK) |
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120 | +#define BCM63268_RESET_PCIE SOFTRESET_63268_PCIE_MASK |
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121 | #define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK |
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122 | +#define BCM63268_RESET_PCIE_CORE SOFTRESET_63268_PCIE_CORE_MASK |
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123 | +#define BCM63268_RESET_PCIE_HARD SOFTRESET_63268_PCIE_HARD_MASK |
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124 | |||
125 | /* |
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126 | * core reset bits |
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127 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |
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128 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |
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129 | @@ -14,6 +14,8 @@ enum bcm63xx_core_reset { |
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130 | BCM63XX_RESET_MPI, |
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131 | BCM63XX_RESET_PCIE, |
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132 | BCM63XX_RESET_PCIE_EXT, |
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133 | + BCM63XX_RESET_PCIE_CORE, |
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134 | + BCM63XX_RESET_PCIE_HARD, |
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135 | }; |
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136 | |||
137 | void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset); |
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138 | --- a/arch/mips/pci/pci-bcm63xx.c |
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139 | +++ b/arch/mips/pci/pci-bcm63xx.c |
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140 | @@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo |
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141 | |||
142 | /* reset the PCIe core */ |
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143 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); |
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144 | + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1); |
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145 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); |
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146 | + if (BCMCPU_IS_6328() || BCMCPU_IS_63268()) { |
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147 | + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1); |
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148 | + mdelay(10); |
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149 | + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0); |
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150 | + } |
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151 | mdelay(10); |
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152 | |||
153 | + bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0); |
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154 | bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); |
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155 | mdelay(10); |
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156 |