OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 8 Dec 2013 01:24:09 +0100 |
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4 | Subject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318 |
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5 | |||
6 | --- |
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7 | arch/mips/bcm63xx/Kconfig | 5 + |
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8 | arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- |
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9 | arch/mips/bcm63xx/clk.c | 8 +- |
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10 | arch/mips/bcm63xx/cpu.c | 53 +++++++++++ |
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11 | arch/mips/bcm63xx/dev-flash.c | 3 + |
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12 | arch/mips/bcm63xx/dev-spi.c | 2 +- |
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13 | arch/mips/bcm63xx/irq.c | 10 ++ |
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14 | arch/mips/bcm63xx/prom.c | 2 +- |
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15 | arch/mips/bcm63xx/reset.c | 24 +++++ |
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16 | arch/mips/bcm63xx/setup.c | 5 +- |
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17 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 107 ++++++++++++++++++++++ |
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18 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 75 ++++++++++++++- |
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19 | arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + |
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20 | 13 files changed, 291 insertions(+), 6 deletions(-) |
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21 | |||
22 | --- a/arch/mips/bcm63xx/Kconfig |
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23 | +++ b/arch/mips/bcm63xx/Kconfig |
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24 | @@ -18,6 +18,11 @@ config BCM63XX_EHCI |
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25 | select USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD |
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26 | select USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD |
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27 | |||
28 | +config BCM63XX_CPU_6318 |
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29 | + bool "support 6318 CPU" |
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30 | + select SYS_HAS_CPU_BMIPS32_3300 |
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31 | + select HW_HAS_PCI |
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32 | + |
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33 | config BCM63XX_CPU_6328 |
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34 | bool "support 6328 CPU" |
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35 | select SYS_HAS_CPU_BMIPS4350 |
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36 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
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37 | +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c |
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38 | @@ -697,7 +697,7 @@ void __init board_prom_init(void) |
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39 | /* read base address of boot chip select (0) |
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40 | * 6328/6362 do not have MPI but boot from a fixed address |
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41 | */ |
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42 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { |
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43 | + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { |
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44 | val = 0x18000000; |
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45 | } else { |
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46 | val = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
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47 | --- a/arch/mips/bcm63xx/clk.c |
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48 | +++ b/arch/mips/bcm63xx/clk.c |
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49 | @@ -288,7 +288,9 @@ static void hsspi_set(struct clk *clk, i |
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50 | { |
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51 | u32 mask; |
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52 | |||
53 | - if (BCMCPU_IS_6328()) |
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54 | + if (BCMCPU_IS_6318()) |
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55 | + mask = CKCTL_6318_HSSPI_EN; |
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56 | + else if (BCMCPU_IS_6328()) |
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57 | mask = CKCTL_6328_HSSPI_EN; |
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58 | else if (BCMCPU_IS_6362()) |
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59 | mask = CKCTL_6362_HSSPI_EN; |
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60 | @@ -443,6 +445,19 @@ static struct clk_lookup bcm3368_clks[] |
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61 | CLKDEV_INIT("bcm63xx_enet.1", "enet", &clk_enet1), |
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62 | }; |
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63 | |||
64 | +static struct clk_lookup bcm6318_clks[] = { |
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65 | + /* fixed rate clocks */ |
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66 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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67 | + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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68 | + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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69 | + /* gated clocks */ |
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70 | + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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71 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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72 | + CLKDEV_INIT(NULL, "usbd", &clk_usbh), |
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73 | + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi), |
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74 | + CLKDEV_INIT(NULL, "pcie", &clk_pcie), |
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75 | +}; |
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76 | + |
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77 | static struct clk_lookup bcm6328_clks[] = { |
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78 | /* fixed rate clocks */ |
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79 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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80 | @@ -564,6 +579,7 @@ static struct clk_lookup bcm63268_clks[] |
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81 | CLKDEV_INIT(NULL, "pcie", &clk_pcie), |
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82 | }; |
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83 | |||
84 | +#define HSSPI_PLL_HZ_6318 250000000 |
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85 | #define HSSPI_PLL_HZ_6328 133333333 |
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86 | #define HSSPI_PLL_HZ_6362 400000000 |
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87 | |||
88 | @@ -573,6 +589,10 @@ static int __init bcm63xx_clk_init(void) |
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89 | case BCM3368_CPU_ID: |
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90 | clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks)); |
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91 | break; |
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92 | + case BCM6318_CPU_ID: |
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93 | + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6318; |
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94 | + clkdev_add_table(bcm6318_clks, ARRAY_SIZE(bcm6318_clks)); |
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95 | + break; |
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96 | case BCM6328_CPU_ID: |
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97 | clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328; |
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98 | clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks)); |
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99 | --- a/arch/mips/bcm63xx/cpu.c |
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100 | +++ b/arch/mips/bcm63xx/cpu.c |
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101 | @@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = { |
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102 | __GEN_CPU_IRQ_TABLE(3368) |
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103 | }; |
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104 | |||
105 | +static const unsigned long bcm6318_regs_base[] = { |
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106 | + __GEN_CPU_REGS_TABLE(6318) |
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107 | +}; |
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108 | + |
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109 | +static const int bcm6318_irqs[] = { |
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110 | + __GEN_CPU_IRQ_TABLE(6318) |
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111 | +}; |
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112 | + |
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113 | static const unsigned long bcm6328_regs_base[] = { |
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114 | __GEN_CPU_REGS_TABLE(6328) |
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115 | }; |
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116 | @@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi |
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117 | return bcm63xx_memory_size; |
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118 | } |
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119 | |||
120 | +#define STRAP_OVERRIDE_BUS_REG 0x0 |
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121 | +#define OVERRIDE_BUS_MIPS_FREQ_SHIFT 23 |
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122 | +#define OVERRIDE_BUS_MIPS_FREQ_MASK (0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT) |
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123 | + |
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124 | static unsigned int detect_cpu_clock(void) |
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125 | { |
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126 | u32 cpu_id = bcm63xx_get_cpu_id(); |
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127 | @@ -142,6 +154,28 @@ static unsigned int detect_cpu_clock(voi |
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128 | case BCM3368_CPU_ID: |
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129 | return 300000000; |
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130 | |||
131 | + case BCM6318_CPU_ID: |
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132 | + { |
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133 | + unsigned int tmp, mips_pll_fcvo; |
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134 | + |
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135 | + tmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG); |
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136 | + |
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137 | + pr_info("strap_override_bus = %08x\n", tmp); |
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138 | + |
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139 | + mips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK) |
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140 | + >> OVERRIDE_BUS_MIPS_FREQ_SHIFT; |
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141 | + |
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142 | + switch (mips_pll_fcvo) { |
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143 | + case 0: |
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144 | + return 166000000; |
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145 | + case 1: |
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146 | + return 400000000; |
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147 | + case 2: |
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148 | + return 250000000; |
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149 | + case 3: |
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150 | + return 333000000; |
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151 | + }; |
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152 | + } |
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153 | case BCM6328_CPU_ID: |
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154 | { |
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155 | unsigned int tmp, mips_pll_fcvo; |
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156 | @@ -297,6 +331,13 @@ static unsigned int detect_memory_size(v |
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157 | unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; |
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158 | u32 val; |
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159 | |||
160 | + if (BCMCPU_IS_6318()) { |
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161 | + val = bcm_sdram_readl(SDRAM_CFG_REG); |
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162 | + val = val & SDRAM_CFG_6318_SPACE_MASK; |
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163 | + val >>= SDRAM_CFG_6318_SPACE_SHIFT; |
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164 | + return 1 << (val + 20); |
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165 | + } |
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166 | + |
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167 | if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) |
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168 | return bcm_ddr_readl(DDR_CSEND_REG) << 24; |
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169 | |||
170 | @@ -343,6 +384,12 @@ void __init bcm63xx_cpu_init(void) |
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171 | |||
172 | switch (current_cpu_type()) { |
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173 | case CPU_BMIPS3300: |
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174 | + if ((read_c0_prid() & 0xff) >= 0x33) { |
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175 | + /* BCM6318 */ |
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176 | + chipid_reg = BCM_6368_PERF_BASE; |
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177 | + break; |
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178 | + } |
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179 | + |
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180 | if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT) |
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181 | __cpu_name[cpu] = "Broadcom BCM6338"; |
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182 | /* fall-through */ |
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183 | @@ -390,6 +437,10 @@ void __init bcm63xx_cpu_init(void) |
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184 | bcm63xx_cpu_variant = bcm63xx_cpu_id; |
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185 | |||
186 | switch (bcm63xx_cpu_id) { |
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187 | + case BCM6318_CPU_ID: |
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188 | + bcm63xx_regs_base = bcm6318_regs_base; |
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189 | + bcm63xx_irqs = bcm6318_irqs; |
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190 | + break; |
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191 | case BCM3368_CPU_ID: |
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192 | bcm63xx_regs_base = bcm3368_regs_base; |
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193 | bcm63xx_irqs = bcm3368_irqs; |
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194 | --- a/arch/mips/bcm63xx/dev-flash.c |
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195 | +++ b/arch/mips/bcm63xx/dev-flash.c |
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196 | @@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t |
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197 | u32 val; |
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198 | |||
199 | switch (bcm63xx_get_cpu_id()) { |
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200 | + case BCM6318_CPU_ID: |
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201 | + /* only support serial flash */ |
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202 | + return BCM63XX_FLASH_TYPE_SERIAL; |
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203 | case BCM6328_CPU_ID: |
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204 | val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); |
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205 | if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) |
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206 | --- a/arch/mips/bcm63xx/dev-spi.c |
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207 | +++ b/arch/mips/bcm63xx/dev-spi.c |
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208 | @@ -38,7 +38,7 @@ static struct platform_device bcm63xx_sp |
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209 | |||
210 | int __init bcm63xx_spi_register(void) |
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211 | { |
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212 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) |
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213 | + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345()) |
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214 | return -ENODEV; |
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215 | |||
216 | spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); |
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217 | --- a/arch/mips/bcm63xx/irq.c |
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218 | +++ b/arch/mips/bcm63xx/irq.c |
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219 | @@ -49,6 +49,19 @@ void __init arch_init_irq(void) |
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220 | ext_irqs[3] = BCM_3368_EXT_IRQ3; |
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221 | ext_shift = 4; |
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222 | break; |
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223 | + case BCM6318_CPU_ID: |
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224 | + periph_bases[0] += PERF_IRQMASK_6318_REG; |
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225 | + periph_irq_count = 1; |
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226 | + periph_width = 4; |
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227 | + |
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228 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318; |
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229 | + ext_irq_count = 4; |
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230 | + ext_irqs[0] = BCM_6318_EXT_IRQ0; |
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231 | + ext_irqs[1] = BCM_6318_EXT_IRQ0; |
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232 | + ext_irqs[2] = BCM_6318_EXT_IRQ0; |
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233 | + ext_irqs[3] = BCM_6318_EXT_IRQ0; |
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234 | + ext_shift = 4; |
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235 | + break; |
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236 | case BCM6328_CPU_ID: |
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237 | periph_bases[0] += PERF_IRQMASK_6328_REG(0); |
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238 | periph_bases[1] += PERF_IRQMASK_6328_REG(1); |
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239 | --- a/arch/mips/bcm63xx/prom.c |
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240 | +++ b/arch/mips/bcm63xx/prom.c |
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241 | @@ -68,7 +68,7 @@ void __init prom_init(void) |
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242 | |||
243 | if (reg & OTP_6328_REG3_TP1_DISABLED) |
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244 | bmips_smp_enabled = 0; |
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245 | - } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { |
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246 | + } else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) { |
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247 | bmips_smp_enabled = 0; |
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248 | } |
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249 | |||
250 | --- a/arch/mips/bcm63xx/reset.c |
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251 | +++ b/arch/mips/bcm63xx/reset.c |
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252 | @@ -43,6 +43,23 @@ |
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253 | #define BCM3368_RESET_PCIE 0 |
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254 | #define BCM3368_RESET_PCIE_EXT 0 |
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255 | |||
256 | + |
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257 | +#define BCM6318_RESET_SPI SOFTRESET_6318_SPI_MASK |
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258 | +#define BCM6318_RESET_ENET 0 |
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259 | +#define BCM6318_RESET_USBH SOFTRESET_6318_USBH_MASK |
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260 | +#define BCM6318_RESET_USBD SOFTRESET_6318_USBS_MASK |
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261 | +#define BCM6318_RESET_DSL 0 |
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262 | +#define BCM6318_RESET_SAR SOFTRESET_6318_SAR_MASK |
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263 | +#define BCM6318_RESET_EPHY SOFTRESET_6318_EPHY_MASK |
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264 | +#define BCM6318_RESET_ENETSW SOFTRESET_6318_ENETSW_MASK |
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265 | +#define BCM6318_RESET_PCM 0 |
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266 | +#define BCM6318_RESET_MPI 0 |
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267 | +#define BCM6318_RESET_PCIE \ |
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268 | + (SOFTRESET_6318_PCIE_MASK | \ |
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269 | + SOFTRESET_6318_PCIE_CORE_MASK | \ |
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270 | + SOFTRESET_6318_PCIE_HARD_MASK) |
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271 | +#define BCM6318_RESET_PCIE_EXT SOFTRESET_6318_PCIE_EXT_MASK |
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272 | + |
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273 | #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK |
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274 | #define BCM6328_RESET_ENET 0 |
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275 | #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK |
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276 | @@ -147,6 +164,10 @@ static const u32 bcm3368_reset_bits[] = |
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277 | __GEN_RESET_BITS_TABLE(3368) |
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278 | }; |
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279 | |||
280 | +static const u32 bcm6318_reset_bits[] = { |
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281 | + __GEN_RESET_BITS_TABLE(6318) |
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282 | +}; |
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283 | + |
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284 | static const u32 bcm6328_reset_bits[] = { |
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285 | __GEN_RESET_BITS_TABLE(6328) |
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286 | }; |
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287 | @@ -183,6 +204,9 @@ static int __init bcm63xx_reset_bits_ini |
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288 | if (BCMCPU_IS_3368()) { |
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289 | reset_reg = PERF_SOFTRESET_6358_REG; |
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290 | bcm63xx_reset_bits = bcm3368_reset_bits; |
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291 | + } else if (BCMCPU_IS_6318()) { |
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292 | + reset_reg = PERF_SOFTRESET_6318_REG; |
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293 | + bcm63xx_reset_bits = bcm6318_reset_bits; |
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294 | } else if (BCMCPU_IS_6328()) { |
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295 | reset_reg = PERF_SOFTRESET_6328_REG; |
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296 | bcm63xx_reset_bits = bcm6328_reset_bits; |
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297 | --- a/arch/mips/bcm63xx/setup.c |
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298 | +++ b/arch/mips/bcm63xx/setup.c |
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299 | @@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void) |
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300 | case BCM3368_CPU_ID: |
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301 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368; |
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302 | break; |
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303 | + case BCM6318_CPU_ID: |
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304 | + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6318; |
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305 | + break; |
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306 | case BCM6328_CPU_ID: |
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307 | perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; |
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308 | break; |
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309 | @@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void) |
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310 | bcm6348_a1_reboot(); |
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311 | |||
312 | pr_info("triggering watchdog soft-reset...\n"); |
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313 | - if (BCMCPU_IS_6328()) { |
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314 | + if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) { |
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315 | bcm_wdt_writel(1, WDT_SOFTRESET_REG); |
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316 | } else { |
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317 | reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); |
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318 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
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319 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
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320 | @@ -10,6 +10,7 @@ |
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321 | * arm mach-types) |
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322 | */ |
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323 | #define BCM3368_CPU_ID 0x3368 |
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324 | +#define BCM6318_CPU_ID 0x6318 |
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325 | #define BCM6328_CPU_ID 0x6328 |
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326 | #define BCM63281_CPU_ID 0x63281 |
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327 | #define BCM63283_CPU_ID 0x63283 |
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328 | @@ -38,6 +39,10 @@ static inline u32 __pure __bcm63xx_get_c |
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329 | case BCM3368_CPU_ID: |
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330 | #endif |
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331 | |||
332 | +#ifdef CONFIG_BCM63XX_CPU_6318 |
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333 | + case BCM6318_CPU_ID: |
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334 | +#endif |
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335 | + |
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336 | #ifdef CONFIG_BCM63XX_CPU_6328 |
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337 | case BCM6328_CPU_ID: |
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338 | #endif |
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339 | @@ -87,6 +92,7 @@ static inline u32 __pure bcm63xx_get_cpu |
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340 | } |
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341 | |||
342 | #define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID) |
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343 | +#define BCMCPU_IS_6318() (bcm63xx_get_cpu_id() == BCM6318_CPU_ID) |
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344 | #define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) |
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345 | #define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) |
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346 | #define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) |
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347 | @@ -98,6 +104,8 @@ static inline u32 __pure bcm63xx_get_cpu |
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348 | |||
349 | #define BCMCPU_VARIANT_IS_3368() \ |
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350 | (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) |
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351 | +#define BCMCPU_VARIANT_IS_6318() \ |
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352 | + (bcm63xx_get_cpu_variant() == BCM6318_CPU_ID) |
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353 | #define BCMCPU_VARIANT_IS_63281() \ |
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354 | (bcm63xx_get_cpu_variant() == BCM63281_CPU_ID) |
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355 | #define BCMCPU_VARIANT_IS_63283() \ |
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356 | @@ -252,6 +260,56 @@ enum bcm63xx_regs_set { |
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357 | #define BCM_3368_MISC_BASE (0xdeadbeef) |
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358 | |||
359 | /* |
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360 | + * 6318 register sets base address |
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361 | + */ |
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362 | +#define BCM_6318_DSL_LMEM_BASE (0xdeadbeef) |
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363 | +#define BCM_6318_PERF_BASE (0xb0000000) |
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364 | +#define BCM_6318_TIMER_BASE (0xb0000040) |
||
365 | +#define BCM_6318_WDT_BASE (0xb0000068) |
||
366 | +#define BCM_6318_UART0_BASE (0xb0000100) |
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367 | +#define BCM_6318_UART1_BASE (0xdeadbeef) |
||
368 | +#define BCM_6318_GPIO_BASE (0xb0000080) |
||
369 | +#define BCM_6318_SPI_BASE (0xdeadbeef) |
||
370 | +#define BCM_6318_HSSPI_BASE (0xb0003000) |
||
371 | +#define BCM_6318_UDC0_BASE (0xdeadbeef) |
||
372 | +#define BCM_6318_USBDMA_BASE (0xb0006800) |
||
373 | +#define BCM_6318_OHCI0_BASE (0xb0005100) |
||
374 | +#define BCM_6318_OHCI_PRIV_BASE (0xdeadbeef) |
||
375 | +#define BCM_6318_USBH_PRIV_BASE (0xb0005200) |
||
376 | +#define BCM_6318_USBD_BASE (0xb0006000) |
||
377 | +#define BCM_6318_MPI_BASE (0xdeadbeef) |
||
378 | +#define BCM_6318_PCMCIA_BASE (0xdeadbeef) |
||
379 | +#define BCM_6318_PCIE_BASE (0xb0010000) |
||
380 | +#define BCM_6318_SDRAM_REGS_BASE (0xdeadbeef) |
||
381 | +#define BCM_6318_DSL_BASE (0xdeadbeef) |
||
382 | +#define BCM_6318_UBUS_BASE (0xdeadbeef) |
||
383 | +#define BCM_6318_ENET0_BASE (0xdeadbeef) |
||
384 | +#define BCM_6318_ENET1_BASE (0xdeadbeef) |
||
385 | +#define BCM_6318_ENETDMA_BASE (0xb0088000) |
||
386 | +#define BCM_6318_ENETDMAC_BASE (0xb0088200) |
||
387 | +#define BCM_6318_ENETDMAS_BASE (0xb0088400) |
||
388 | +#define BCM_6318_ENETSW_BASE (0xb0080000) |
||
389 | +#define BCM_6318_EHCI0_BASE (0xb0005000) |
||
390 | +#define BCM_6318_SDRAM_BASE (0xb0004000) |
||
391 | +#define BCM_6318_MEMC_BASE (0xdeadbeef) |
||
392 | +#define BCM_6318_DDR_BASE (0xdeadbeef) |
||
393 | +#define BCM_6318_M2M_BASE (0xdeadbeef) |
||
394 | +#define BCM_6318_ATM_BASE (0xdeadbeef) |
||
395 | +#define BCM_6318_XTM_BASE (0xdeadbeef) |
||
396 | +#define BCM_6318_XTMDMA_BASE (0xb000c000) |
||
397 | +#define BCM_6318_XTMDMAC_BASE (0xdeadbeef) |
||
398 | +#define BCM_6318_XTMDMAS_BASE (0xdeadbeef) |
||
399 | +#define BCM_6318_PCM_BASE (0xdeadbeef) |
||
400 | +#define BCM_6318_PCMDMA_BASE (0xdeadbeef) |
||
401 | +#define BCM_6318_PCMDMAC_BASE (0xdeadbeef) |
||
402 | +#define BCM_6318_PCMDMAS_BASE (0xdeadbeef) |
||
403 | +#define BCM_6318_RNG_BASE (0xdeadbeef) |
||
404 | +#define BCM_6318_MISC_BASE (0xb0000280) |
||
405 | +#define BCM_6318_OTP_BASE (0xdeadbeef) |
||
406 | + |
||
407 | +#define BCM_6318_STRAP_BASE (0xb0000900) |
||
408 | + |
||
409 | +/* |
||
410 | * 6328 register sets base address |
||
411 | */ |
||
412 | #define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) |
||
413 | @@ -774,6 +832,55 @@ enum bcm63xx_irq { |
||
414 | #define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) |
||
415 | #define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) |
||
416 | |||
417 | +/* |
||
418 | + * 6318 irqs |
||
419 | + */ |
||
420 | +#define BCM_6318_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) |
||
421 | +#define BCM_6318_VERY_HIGH_IRQ_BASE (BCM_6318_HIGH_IRQ_BASE + 32) |
||
422 | + |
||
423 | +#define BCM_6318_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) |
||
424 | +#define BCM_6318_SPI_IRQ 0 |
||
425 | +#define BCM_6318_UART0_IRQ (IRQ_INTERNAL_BASE + 28) |
||
426 | +#define BCM_6318_UART1_IRQ 0 |
||
427 | +#define BCM_6318_DSL_IRQ (IRQ_INTERNAL_BASE + 21) |
||
428 | +#define BCM_6318_UDC0_IRQ 0 |
||
429 | +#define BCM_6318_ENET0_IRQ 0 |
||
430 | +#define BCM_6318_ENET1_IRQ 0 |
||
431 | +#define BCM_6318_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
||
432 | +#define BCM_6318_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) |
||
433 | +#define BCM_6318_OHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 9) |
||
434 | +#define BCM_6318_EHCI0_IRQ (BCM_6318_HIGH_IRQ_BASE + 10) |
||
435 | +#define BCM_6318_USBD_IRQ (IRQ_INTERNAL_BASE + 4) |
||
436 | +#define BCM_6318_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) |
||
437 | +#define BCM_6318_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) |
||
438 | +#define BCM_6318_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) |
||
439 | +#define BCM_6318_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) |
||
440 | +#define BCM_6318_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) |
||
441 | +#define BCM_6318_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) |
||
442 | +#define BCM_6318_PCMCIA_IRQ 0 |
||
443 | +#define BCM_6318_ENET0_RXDMA_IRQ 0 |
||
444 | +#define BCM_6318_ENET0_TXDMA_IRQ 0 |
||
445 | +#define BCM_6318_ENET1_RXDMA_IRQ 0 |
||
446 | +#define BCM_6318_ENET1_TXDMA_IRQ 0 |
||
447 | +#define BCM_6318_PCI_IRQ (IRQ_INTERNAL_BASE + 23) |
||
448 | +#define BCM_6318_ATM_IRQ 0 |
||
449 | +#define BCM_6318_ENETSW_RXDMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 0) |
||
450 | +#define BCM_6318_ENETSW_RXDMA1_IRQ (BCM_6318_HIGH_IRQ_BASE + 1) |
||
451 | +#define BCM_6318_ENETSW_RXDMA2_IRQ (BCM_6318_HIGH_IRQ_BASE + 2) |
||
452 | +#define BCM_6318_ENETSW_RXDMA3_IRQ (BCM_6318_HIGH_IRQ_BASE + 3) |
||
453 | +#define BCM_6318_ENETSW_TXDMA0_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 10) |
||
454 | +#define BCM_6318_ENETSW_TXDMA1_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 11) |
||
455 | +#define BCM_6318_ENETSW_TXDMA2_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 12) |
||
456 | +#define BCM_6318_ENETSW_TXDMA3_IRQ (BCM_6318_VERY_HIGH_IRQ_BASE + 13) |
||
457 | +#define BCM_6318_XTM_IRQ (BCM_6318_HIGH_IRQ_BASE + 31) |
||
458 | +#define BCM_6318_XTM_DMA0_IRQ (BCM_6318_HIGH_IRQ_BASE + 11) |
||
459 | + |
||
460 | +#define BCM_6318_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) |
||
461 | +#define BCM_6318_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) |
||
462 | +#define BCM_6318_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) |
||
463 | +#define BCM_6318_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) |
||
464 | +#define BCM_6318_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) |
||
465 | +#define BCM_6318_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) |
||
466 | |||
467 | /* |
||
468 | * 6328 irqs |
||
469 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
||
470 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
||
471 | @@ -52,6 +52,39 @@ |
||
472 | CKCTL_3368_EMUSB_EN | \ |
||
473 | CKCTL_3368_USBU_EN) |
||
474 | |||
475 | +#define CKCTL_6318_ADSL_ASB_EN (1 << 0) |
||
476 | +#define CKCTL_6318_USB_ASB_EN (1 << 1) |
||
477 | +#define CKCTL_6318_MIPS_ASB_EN (1 << 2) |
||
478 | +#define CKCTL_6318_PCIE_ASB_EN (1 << 3) |
||
479 | +#define CKCTL_6318_PHYMIPS_ASB_EN (1 << 4) |
||
480 | +#define CKCTL_6318_ROBOSW_ASB_EN (1 << 5) |
||
481 | +#define CKCTL_6318_SAR_ASB_EN (1 << 6) |
||
482 | +#define CKCTL_6318_SDR_ASB_EN (1 << 7) |
||
483 | +#define CKCTL_6318_SWREG_ASB_EN (1 << 8) |
||
484 | +#define CKCTL_6318_PERIPH_ASB_EN (1 << 9) |
||
485 | +#define CKCTL_6318_CPUBUS160_EN (1 << 10) |
||
486 | +#define CKCTL_6318_ADSL_EN (1 << 11) |
||
487 | +#define CKCTL_6318_SAR125_EN (1 << 12) |
||
488 | +#define CKCTL_6318_MIPS_EN (1 << 13) |
||
489 | +#define CKCTL_6318_PCIE_EN (1 << 14) |
||
490 | +#define CKCTL_6318_ROBOSW250_EN (1 << 16) |
||
491 | +#define CKCTL_6318_ROBOSW025_EN (1 << 17) |
||
492 | +#define CKCTL_6318_SDR_EN (1 << 19) |
||
493 | +#define CKCTL_6318_USB_EN (1 << 20) /* both device and host */ |
||
494 | +#define CKCTL_6318_HSSPI_EN (1 << 25) |
||
495 | +#define CKCTL_6318_PCIE25_EN (1 << 27) |
||
496 | +#define CKCTL_6318_PHYMIPS_EN (1 << 28) |
||
497 | +#define CKCTL_6318_ADSL_AFE_EN (1 << 29) |
||
498 | +#define CKCTL_6318_ADSL_QPROC_EN (1 << 30) |
||
499 | + |
||
500 | +#define CKCTL_6318_ALL_SAFE_EN (CKCTL_6318_PHYMIPS_EN | \ |
||
501 | + CKCTL_6318_ADSL_QPROC_EN | \ |
||
502 | + CKCTL_6318_ADSL_AFE_EN | \ |
||
503 | + CKCTL_6318_ADSL_EN | \ |
||
504 | + CKCTL_6318_SAR_EN | \ |
||
505 | + CKCTL_6318_USB_EN | \ |
||
506 | + CKCTL_6318_PCIE_EN) |
||
507 | + |
||
508 | #define CKCTL_6328_PHYMIPS_EN (1 << 0) |
||
509 | #define CKCTL_6328_ADSL_QPROC_EN (1 << 1) |
||
510 | #define CKCTL_6328_ADSL_AFE_EN (1 << 2) |
||
511 | @@ -259,12 +292,27 @@ |
||
512 | CKCTL_63268_TBUS_EN | \ |
||
513 | CKCTL_63268_ROBOSW250_EN) |
||
514 | |||
515 | +/* UBUS Clock Control register */ |
||
516 | +#define PERF_UB_CKCTL_REG 0x10 |
||
517 | + |
||
518 | +#define UB_CKCTL_6318_ADSL_EN (1 << 0) |
||
519 | +#define UB_CKCTL_6318_ARB_EN (1 << 1) |
||
520 | +#define UB_CKCTL_6318_MIPS_EN (1 << 2) |
||
521 | +#define UB_CKCTL_6318_PCIE_EN (1 << 3) |
||
522 | +#define UB_CKCTL_6318_PERIPH_EN (1 << 4) |
||
523 | +#define UB_CKCTL_6318_PHYMIPS_EN (1 << 5) |
||
524 | +#define UB_CKCTL_6318_ROBOSW_EN (1 << 6) |
||
525 | +#define UB_CKCTL_6318_SAR_EN (1 << 7) |
||
526 | +#define UB_CKCTL_6318_SDR_EN (1 << 8) |
||
527 | +#define UB_CKCTL_6318_USB_EN (1 << 9) |
||
528 | + |
||
529 | /* System PLL Control register */ |
||
530 | #define PERF_SYS_PLL_CTL_REG 0x8 |
||
531 | #define SYS_PLL_SOFT_RESET 0x1 |
||
532 | |||
533 | /* Interrupt Mask register */ |
||
534 | #define PERF_IRQMASK_3368_REG 0xc |
||
535 | +#define PERF_IRQMASK_6318_REG 0x20 |
||
536 | #define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10) |
||
537 | #define PERF_IRQMASK_6338_REG 0xc |
||
538 | #define PERF_IRQMASK_6345_REG 0xc |
||
539 | @@ -276,6 +324,7 @@ |
||
540 | |||
541 | /* Interrupt Status register */ |
||
542 | #define PERF_IRQSTAT_3368_REG 0x10 |
||
543 | +#define PERF_IRQSTAT_6318_REG 0x30 |
||
544 | #define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10) |
||
545 | #define PERF_IRQSTAT_6338_REG 0x10 |
||
546 | #define PERF_IRQSTAT_6345_REG 0x10 |
||
547 | @@ -287,6 +336,7 @@ |
||
548 | |||
549 | /* External Interrupt Configuration register */ |
||
550 | #define PERF_EXTIRQ_CFG_REG_3368 0x14 |
||
551 | +#define PERF_EXTIRQ_CFG_REG_6318 0x18 |
||
552 | #define PERF_EXTIRQ_CFG_REG_6328 0x18 |
||
553 | #define PERF_EXTIRQ_CFG_REG_6338 0x14 |
||
554 | #define PERF_EXTIRQ_CFG_REG_6345 0x14 |
||
555 | @@ -321,6 +371,7 @@ |
||
556 | |||
557 | /* Soft Reset register */ |
||
558 | #define PERF_SOFTRESET_REG 0x28 |
||
559 | +#define PERF_SOFTRESET_6318_REG 0x10 |
||
560 | #define PERF_SOFTRESET_6328_REG 0x10 |
||
561 | #define PERF_SOFTRESET_6358_REG 0x34 |
||
562 | #define PERF_SOFTRESET_6362_REG 0x10 |
||
563 | @@ -334,6 +385,18 @@ |
||
564 | #define SOFTRESET_3368_USBS_MASK (1 << 11) |
||
565 | #define SOFTRESET_3368_PCM_MASK (1 << 13) |
||
566 | |||
567 | +#define SOFTRESET_6318_SPI_MASK (1 << 0) |
||
568 | +#define SOFTRESET_6318_EPHY_MASK (1 << 1) |
||
569 | +#define SOFTRESET_6318_SAR_MASK (1 << 2) |
||
570 | +#define SOFTRESET_6318_ENETSW_MASK (1 << 3) |
||
571 | +#define SOFTRESET_6318_USBS_MASK (1 << 4) |
||
572 | +#define SOFTRESET_6318_USBH_MASK (1 << 5) |
||
573 | +#define SOFTRESET_6318_PCIE_CORE_MASK (1 << 6) |
||
574 | +#define SOFTRESET_6318_PCIE_MASK (1 << 7) |
||
575 | +#define SOFTRESET_6318_PCIE_EXT_MASK (1 << 8) |
||
576 | +#define SOFTRESET_6318_PCIE_HARD_MASK (1 << 9) |
||
577 | +#define SOFTRESET_6318_ADSL_MASK (1 << 10) |
||
578 | + |
||
579 | #define SOFTRESET_6328_SPI_MASK (1 << 0) |
||
580 | #define SOFTRESET_6328_EPHY_MASK (1 << 1) |
||
581 | #define SOFTRESET_6328_SAR_MASK (1 << 2) |
||
582 | @@ -505,8 +568,17 @@ |
||
583 | #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) |
||
584 | #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) |
||
585 | |||
586 | +#define TIMER_IRQMASK_6318_REG 0x0 |
||
587 | +#define TIMER_IRQSTAT_6318_REG 0x4 |
||
588 | +#define IRQSTATMASK_TIMER0 (1 << 0) |
||
589 | +#define IRQSTATMASK_TIMER1 (1 << 1) |
||
590 | +#define IRQSTATMASK_TIMER2 (1 << 2) |
||
591 | +#define IRQSTATMASK_TIMER3 (1 << 3) |
||
592 | +#define IRQSTATMASK_WDT (1 << 4) |
||
593 | + |
||
594 | /* Timer control register */ |
||
595 | #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) |
||
596 | +#define TIMER_CTRx_6318_REG(x) (0x8 + (x * 4)) |
||
597 | #define TIMER_CTL0_REG 0x4 |
||
598 | #define TIMER_CTL1_REG 0x8 |
||
599 | #define TIMER_CTL2_REG 0xC |
||
600 | @@ -1253,6 +1325,8 @@ |
||
601 | #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) |
||
602 | #define SDRAM_CFG_BANK_SHIFT 13 |
||
603 | #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) |
||
604 | +#define SDRAM_CFG_6318_SPACE_SHIFT 4 |
||
605 | +#define SDRAM_CFG_6318_SPACE_MASK (0xf << SDRAM_CFG_6318_SPACE_SHIFT) |
||
606 | |||
607 | #define SDRAM_MBASE_REG 0xc |
||
608 | |||
609 | --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h |
||
610 | +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h |
||
611 | @@ -22,6 +22,7 @@ static inline int is_bcm63xx_internal_re |
||
612 | if (offset >= 0xfff00000) |
||
613 | return 1; |
||
614 | break; |
||
615 | + case BCM6318_CPU_ID: |
||
616 | case BCM6328_CPU_ID: |
||
617 | case BCM6362_CPU_ID: |
||
618 | case BCM6368_CPU_ID: |
||
619 | --- a/arch/mips/bcm63xx/dev-hsspi.c |
||
620 | +++ b/arch/mips/bcm63xx/dev-hsspi.c |
||
621 | @@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs |
||
622 | |||
623 | int __init bcm63xx_hsspi_register(void) |
||
624 | { |
||
625 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) |
||
626 | + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && |
||
627 | + !BCMCPU_IS_63268()) |
||
628 | return -ENODEV; |
||
629 | |||
630 | spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); |
||
631 | --- a/arch/mips/bcm63xx/dev-usb-usbd.c |
||
632 | +++ b/arch/mips/bcm63xx/dev-usb-usbd.c |
||
633 | @@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s |
||
634 | IRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 }; |
||
635 | int i; |
||
636 | |||
637 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6368()) |
||
638 | + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368()) |
||
639 | return 0; |
||
640 | |||
641 | usbd_resources[0].start = bcm63xx_regset_address(RSET_USBD); |
||
642 | --- a/arch/mips/bcm63xx/dev-enet.c |
||
643 | +++ b/arch/mips/bcm63xx/dev-enet.c |
||
644 | @@ -176,8 +176,8 @@ static int __init register_shared(void) |
||
645 | else |
||
646 | shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; |
||
647 | |||
648 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || |
||
649 | - BCMCPU_IS_63268()) |
||
650 | + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || |
||
651 | + BCMCPU_IS_6368() || BCMCPU_IS_63268()) |
||
652 | chan_count = 32; |
||
653 | else if (BCMCPU_IS_6345()) |
||
654 | chan_count = 8; |
||
655 | @@ -285,8 +285,8 @@ bcm63xx_enetsw_register(const struct bcm |
||
656 | { |
||
657 | int ret; |
||
658 | |||
659 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && |
||
660 | - !BCMCPU_IS_63268()) |
||
661 | + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() && |
||
662 | + !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) |
||
663 | return -ENODEV; |
||
664 | |||
665 | ret = register_shared(); |
||
666 | @@ -303,7 +303,7 @@ bcm63xx_enetsw_register(const struct bcm |
||
667 | |||
668 | memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd)); |
||
669 | |||
670 | - if (BCMCPU_IS_6328()) |
||
671 | + if (BCMCPU_IS_6318() || BCMCPU_IS_6328()) |
||
672 | enetsw_pd.num_ports = ENETSW_PORTS_6328; |
||
673 | else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) |
||
674 | enetsw_pd.num_ports = ENETSW_PORTS_6368; |
||
675 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |
||
676 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |
||
677 | @@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void); |
||
678 | static inline unsigned long bcm63xx_gpio_count(void) |
||
679 | { |
||
680 | switch (bcm63xx_get_cpu_id()) { |
||
681 | + case BCM6318_CPU_ID: |
||
682 | + return 50; |
||
683 | case BCM6328_CPU_ID: |
||
684 | return 32; |
||
685 | case BCM3368_CPU_ID: |
||
686 | --- a/arch/mips/bcm63xx/dev-usb-ehci.c |
||
687 | +++ b/arch/mips/bcm63xx/dev-usb-ehci.c |
||
688 | @@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh |
||
689 | |||
690 | int __init bcm63xx_ehci_register(void) |
||
691 | { |
||
692 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) |
||
693 | + if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && |
||
694 | + !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) |
||
695 | return 0; |
||
696 | |||
697 | ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); |