OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sat, 7 Dec 2013 17:14:17 +0100 |
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4 | Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268 |
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5 | |||
6 | Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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7 | --- |
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8 | arch/mips/bcm63xx/Kconfig | 5 + |
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9 | arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +- |
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10 | arch/mips/bcm63xx/clk.c | 25 ++++- |
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11 | arch/mips/bcm63xx/cpu.c | 59 +++++++++- |
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12 | arch/mips/bcm63xx/dev-flash.c | 6 + |
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13 | arch/mips/bcm63xx/dev-spi.c | 4 +- |
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14 | arch/mips/bcm63xx/irq.c | 20 +++- |
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15 | arch/mips/bcm63xx/reset.c | 21 ++++ |
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16 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++ |
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17 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 + |
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18 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++ |
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19 | arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 + |
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20 | 12 files changed, 342 insertions(+), 12 deletions(-) |
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21 | |||
22 | --- a/arch/mips/bcm63xx/Kconfig |
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23 | +++ b/arch/mips/bcm63xx/Kconfig |
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24 | @@ -60,6 +60,11 @@ config BCM63XX_CPU_6368 |
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25 | select HW_HAS_PCI |
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26 | select BCM63XX_OHCI |
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27 | select BCM63XX_EHCI |
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28 | + |
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29 | +config BCM63XX_CPU_63268 |
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30 | + bool "support 63268 CPU" |
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31 | + select SYS_HAS_CPU_BMIPS4350 |
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32 | + select HW_HAS_PCI |
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33 | endmenu |
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34 | |||
35 | source "arch/mips/bcm63xx/boards/Kconfig" |
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36 | --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c |
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37 | +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c |
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3 | office | 38 | @@ -713,7 +713,7 @@ void __init board_prom_init(void) |
1 | office | 39 | /* read base address of boot chip select (0) |
40 | * 6328/6362 do not have MPI but boot from a fixed address |
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41 | */ |
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42 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { |
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43 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) { |
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44 | val = 0x18000000; |
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45 | } else { |
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46 | val = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
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47 | --- a/arch/mips/bcm63xx/clk.c |
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48 | +++ b/arch/mips/bcm63xx/clk.c |
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49 | @@ -168,6 +168,8 @@ static void enetsw_set(struct clk *clk, |
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50 | clk_disable_unlocked(&clk_swpkt_sar); |
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51 | } |
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52 | bcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable); |
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53 | + } else if (BCMCPU_IS_63268()) { |
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54 | + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable); |
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55 | } else { |
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56 | return; |
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57 | } |
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58 | @@ -213,6 +215,8 @@ static void usbh_set(struct clk *clk, in |
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59 | bcm_hwclock_set(CKCTL_6362_USBH_EN, enable); |
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60 | else if (BCMCPU_IS_6368()) |
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61 | bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); |
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62 | + else if (BCMCPU_IS_63268()) |
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63 | + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); |
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64 | else |
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65 | return; |
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66 | |||
67 | @@ -235,6 +239,8 @@ static void usbd_set(struct clk *clk, in |
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68 | bcm_hwclock_set(CKCTL_6362_USBD_EN, enable); |
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69 | else if (BCMCPU_IS_6368()) |
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70 | bcm_hwclock_set(CKCTL_6368_USBD_EN, enable); |
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71 | + else if (BCMCPU_IS_63268()) |
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72 | + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable); |
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73 | else |
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74 | return; |
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75 | |||
76 | @@ -261,9 +267,13 @@ static void spi_set(struct clk *clk, int |
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77 | mask = CKCTL_6358_SPI_EN; |
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78 | else if (BCMCPU_IS_6362()) |
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79 | mask = CKCTL_6362_SPI_EN; |
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80 | - else |
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81 | - /* BCMCPU_IS_6368 */ |
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82 | + else if (BCMCPU_IS_6368()) |
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83 | mask = CKCTL_6368_SPI_EN; |
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84 | + else if (BCMCPU_IS_63268()) |
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85 | + mask = CKCTL_63268_SPI_EN; |
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86 | + else |
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87 | + return; |
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88 | + |
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89 | bcm_hwclock_set(mask, enable); |
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90 | } |
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91 | |||
92 | @@ -282,6 +292,8 @@ static void hsspi_set(struct clk *clk, i |
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93 | mask = CKCTL_6328_HSSPI_EN; |
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94 | else if (BCMCPU_IS_6362()) |
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95 | mask = CKCTL_6362_HSSPI_EN; |
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96 | + else if (BCMCPU_IS_63268()) |
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97 | + mask = CKCTL_63268_HSSPI_EN; |
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98 | else |
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99 | return; |
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100 | |||
101 | @@ -351,6 +363,8 @@ static void pcie_set(struct clk *clk, in |
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102 | bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable); |
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103 | else if (BCMCPU_IS_6362()) |
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104 | bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable); |
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105 | + else if (BCMCPU_IS_63268()) |
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106 | + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable); |
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107 | } |
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108 | |||
109 | static struct clk clk_pcie = { |
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110 | @@ -535,6 +549,21 @@ static struct clk_lookup bcm6368_clks[] |
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111 | CLKDEV_INIT(NULL, "ipsec", &clk_ipsec), |
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112 | }; |
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113 | |||
114 | +static struct clk_lookup bcm63268_clks[] = { |
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115 | + /* fixed rate clocks */ |
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116 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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117 | + CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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118 | + CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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119 | + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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120 | + /* gated clocks */ |
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121 | + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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122 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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123 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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124 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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125 | + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi), |
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126 | + CLKDEV_INIT(NULL, "pcie", &clk_pcie), |
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127 | +}; |
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128 | + |
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129 | #define HSSPI_PLL_HZ_6328 133333333 |
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130 | #define HSSPI_PLL_HZ_6362 400000000 |
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131 | |||
132 | @@ -567,6 +596,10 @@ static int __init bcm63xx_clk_init(void) |
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133 | case BCM6368_CPU_ID: |
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134 | clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks)); |
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135 | break; |
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136 | + case BCM63268_CPU_ID: |
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137 | + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362; |
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138 | + clkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks)); |
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139 | + break; |
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140 | } |
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141 | |||
142 | return 0; |
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143 | --- a/arch/mips/bcm63xx/cpu.c |
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144 | +++ b/arch/mips/bcm63xx/cpu.c |
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145 | @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = { |
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146 | |||
147 | }; |
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148 | |||
149 | +static const unsigned long bcm63268_regs_base[] = { |
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150 | + __GEN_CPU_REGS_TABLE(63268) |
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151 | +}; |
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152 | + |
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153 | +static const int bcm63268_irqs[] = { |
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154 | + __GEN_CPU_IRQ_TABLE(63268) |
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155 | + |
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156 | +}; |
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157 | + |
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158 | u32 bcm63xx_get_cpu_variant(void) |
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159 | { |
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160 | return bcm63xx_cpu_variant; |
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161 | @@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi |
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162 | |||
163 | return (((64 * 1000000) / p1) * p2 * ndiv) / m1; |
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164 | } |
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165 | + case BCM63268_CPU_ID: |
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166 | + { |
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167 | + unsigned int tmp, mips_pll_fcvo; |
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168 | + |
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169 | + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG); |
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170 | + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >> |
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171 | + STRAPBUS_63268_FCVO_SHIFT; |
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172 | + switch (mips_pll_fcvo) { |
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173 | + case 0x3: |
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174 | + case 0xe: |
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175 | + return 320000000; |
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176 | + case 0xa: |
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177 | + return 333000000; |
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178 | + case 0x2: |
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179 | + case 0xb: |
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180 | + case 0xf: |
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181 | + return 400000000; |
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182 | + default: |
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183 | + return 0; |
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184 | + } |
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185 | + } |
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186 | |||
187 | default: |
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188 | panic("Failed to detect clock for CPU with id=%04X\n", cpu_id); |
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189 | @@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v |
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190 | unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; |
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191 | u32 val; |
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192 | |||
193 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) |
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194 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) |
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195 | return bcm_ddr_readl(DDR_CSEND_REG) << 24; |
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196 | |||
197 | if (BCMCPU_IS_6345()) { |
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198 | @@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void) |
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199 | unsigned int tmp; |
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200 | unsigned int cpu = smp_processor_id(); |
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201 | u32 chipid_reg; |
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202 | + bool long_chipid = false; |
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203 | u8 __maybe_unused varid = 0; |
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204 | |||
205 | /* soc registers location depends on cpu type */ |
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206 | @@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void) |
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207 | case 0x10: |
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208 | chipid_reg = BCM_6345_PERF_BASE; |
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209 | break; |
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210 | + case 0x80: |
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211 | + long_chipid = true; |
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212 | + /* fall-through */ |
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213 | default: |
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214 | chipid_reg = BCM_6368_PERF_BASE; |
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215 | break; |
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216 | @@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void) |
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217 | break; |
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218 | } |
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219 | |||
220 | + |
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221 | /* |
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222 | * really early to panic, but delaying panic would not help since we |
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223 | * will never get any working console |
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224 | @@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void) |
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225 | |||
226 | /* read out CPU type */ |
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227 | tmp = bcm_readl(chipid_reg); |
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228 | - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; |
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229 | - bcm63xx_cpu_variant = bcm63xx_cpu_id; |
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230 | + |
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231 | + if (long_chipid) { |
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232 | + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK; |
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233 | + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT; |
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234 | + } else { |
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235 | + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; |
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236 | + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; |
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237 | + } |
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238 | + |
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239 | bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; |
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240 | - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT; |
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241 | + bcm63xx_cpu_variant = bcm63xx_cpu_id; |
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242 | |||
243 | switch (bcm63xx_cpu_id) { |
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244 | case BCM3368_CPU_ID: |
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245 | @@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void) |
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246 | /* BCM6369 is a BCM6368 without xDSL, so treat it the same */ |
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247 | bcm63xx_cpu_id = BCM6368_CPU_ID; |
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248 | break; |
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249 | + case BCM63168_CPU_ID: |
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250 | + case BCM63169_CPU_ID: |
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251 | + case BCM63268_CPU_ID: |
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252 | + case BCM63269_CPU_ID: |
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253 | + bcm63xx_regs_base = bcm63268_regs_base; |
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254 | + bcm63xx_irqs = bcm63268_irqs; |
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255 | + |
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256 | + bcm63xx_cpu_id = BCM63268_CPU_ID; |
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257 | + break; |
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258 | default: |
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259 | panic("unsupported broadcom CPU %x", bcm63xx_cpu_id); |
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260 | break; |
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261 | --- a/arch/mips/bcm63xx/dev-flash.c |
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262 | +++ b/arch/mips/bcm63xx/dev-flash.c |
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263 | @@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t |
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264 | case STRAPBUS_6368_BOOT_SEL_PARALLEL: |
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265 | return BCM63XX_FLASH_TYPE_PARALLEL; |
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266 | } |
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267 | + case BCM63268_CPU_ID: |
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268 | + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG); |
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269 | + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL) |
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270 | + return BCM63XX_FLASH_TYPE_SERIAL; |
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271 | + else |
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272 | + return BCM63XX_FLASH_TYPE_NAND; |
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273 | default: |
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274 | return -EINVAL; |
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275 | } |
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276 | --- a/arch/mips/bcm63xx/dev-spi.c |
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277 | +++ b/arch/mips/bcm63xx/dev-spi.c |
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278 | @@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void) |
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279 | } |
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280 | |||
281 | if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() || |
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282 | - BCMCPU_IS_6368()) { |
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283 | + BCMCPU_IS_6368() || BCMCPU_IS_63268()) { |
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284 | bcm63xx_spi_device.name = "bcm6358-spi", |
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285 | spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; |
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286 | } |
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287 | --- a/arch/mips/bcm63xx/irq.c |
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288 | +++ b/arch/mips/bcm63xx/irq.c |
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289 | @@ -150,6 +150,20 @@ void __init arch_init_irq(void) |
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290 | ext_irqs[5] = BCM_6368_EXT_IRQ5; |
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291 | ext_shift = 4; |
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292 | break; |
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293 | + case BCM63268_CPU_ID: |
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294 | + periph_bases[0] += PERF_IRQMASK_63268_REG(0); |
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295 | + periph_bases[1] += PERF_IRQMASK_63268_REG(1); |
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296 | + periph_irq_count = 2; |
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297 | + periph_width = 4; |
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298 | + |
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299 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268; |
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300 | + ext_irq_count = 4; |
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301 | + ext_irqs[0] = BCM_63268_EXT_IRQ0; |
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302 | + ext_irqs[1] = BCM_63268_EXT_IRQ1; |
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303 | + ext_irqs[2] = BCM_63268_EXT_IRQ2; |
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304 | + ext_irqs[3] = BCM_63268_EXT_IRQ3; |
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305 | + ext_shift = 4; |
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306 | + break; |
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307 | default: |
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308 | BUG(); |
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309 | } |
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310 | --- a/arch/mips/bcm63xx/reset.c |
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311 | +++ b/arch/mips/bcm63xx/reset.c |
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312 | @@ -125,6 +125,20 @@ |
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313 | #define BCM6368_RESET_PCIE 0 |
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314 | #define BCM6368_RESET_PCIE_EXT 0 |
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315 | |||
316 | +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK |
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317 | +#define BCM63268_RESET_ENET 0 |
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318 | +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK |
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319 | +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK |
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320 | +#define BCM63268_RESET_DSL 0 |
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321 | +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK |
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322 | +#define BCM63268_RESET_EPHY 0 |
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323 | +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK |
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324 | +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK |
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325 | +#define BCM63268_RESET_MPI 0 |
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326 | +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \ |
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327 | + SOFTRESET_63268_PCIE_CORE_MASK) |
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328 | +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK |
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329 | + |
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330 | /* |
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331 | * core reset bits |
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332 | */ |
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333 | @@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] = |
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334 | __GEN_RESET_BITS_TABLE(6368) |
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335 | }; |
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336 | |||
337 | +static const u32 bcm63268_reset_bits[] = { |
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338 | + __GEN_RESET_BITS_TABLE(63268) |
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339 | +}; |
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340 | + |
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341 | const u32 *bcm63xx_reset_bits; |
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342 | static int reset_reg; |
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343 | |||
344 | @@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini |
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345 | } else if (BCMCPU_IS_6368()) { |
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346 | reset_reg = PERF_SOFTRESET_6368_REG; |
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347 | bcm63xx_reset_bits = bcm6368_reset_bits; |
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348 | + } else if (BCMCPU_IS_63268()) { |
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349 | + reset_reg = PERF_SOFTRESET_63268_REG; |
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350 | + bcm63xx_reset_bits = bcm63268_reset_bits; |
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351 | } |
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352 | |||
353 | return 0; |
||
354 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
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355 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |
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356 | @@ -21,6 +21,10 @@ |
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357 | #define BCM6362_CPU_ID 0x6362 |
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358 | #define BCM6368_CPU_ID 0x6368 |
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359 | #define BCM6369_CPU_ID 0x6369 |
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360 | +#define BCM63168_CPU_ID 0x63168 |
||
361 | +#define BCM63169_CPU_ID 0x63169 |
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362 | +#define BCM63268_CPU_ID 0x63268 |
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363 | +#define BCM63269_CPU_ID 0x63269 |
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364 | |||
365 | void __init bcm63xx_cpu_init(void); |
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366 | u32 bcm63xx_get_cpu_variant(void); |
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367 | @@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c |
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368 | #ifdef CONFIG_BCM63XX_CPU_6368 |
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369 | case BCM6368_CPU_ID: |
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370 | #endif |
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371 | + |
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372 | +#ifdef CONFIG_BCM63XX_CPU_63268 |
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373 | + case BCM63268_CPU_ID: |
||
374 | +#endif |
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375 | break; |
||
376 | default: |
||
377 | unreachable(); |
||
378 | @@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu |
||
379 | #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) |
||
380 | #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID) |
||
381 | #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) |
||
382 | +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID) |
||
383 | |||
384 | #define BCMCPU_VARIANT_IS_3368() \ |
||
385 | (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID) |
||
386 | @@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu |
||
387 | (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID) |
||
388 | #define BCMCPU_VARIANT_IS_6369() \ |
||
389 | (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID) |
||
390 | +#define BCMCPU_VARIANT_IS_63168() \ |
||
391 | + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID) |
||
392 | +#define BCMCPU_VARIANT_IS_63169() \ |
||
393 | + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID) |
||
394 | +#define BCMCPU_VARIANT_IS_63268() \ |
||
395 | + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID) |
||
396 | +#define BCMCPU_VARIANT_IS_63269() \ |
||
397 | + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID) |
||
398 | |||
399 | /* |
||
400 | * While registers sets are (mostly) the same across 63xx CPU, base |
||
401 | @@ -573,6 +590,52 @@ enum bcm63xx_regs_set { |
||
402 | #define BCM_6368_RNG_BASE (0xb0004180) |
||
403 | #define BCM_6368_MISC_BASE (0xdeadbeef) |
||
404 | |||
405 | +/* |
||
406 | + * 63268 register sets base address |
||
407 | + */ |
||
408 | +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef) |
||
409 | +#define BCM_63268_PERF_BASE (0xb0000000) |
||
410 | +#define BCM_63268_TIMER_BASE (0xb0000080) |
||
411 | +#define BCM_63268_WDT_BASE (0xb000009c) |
||
412 | +#define BCM_63268_UART0_BASE (0xb0000180) |
||
413 | +#define BCM_63268_UART1_BASE (0xb00001a0) |
||
414 | +#define BCM_63268_GPIO_BASE (0xb00000c0) |
||
415 | +#define BCM_63268_SPI_BASE (0xb0000800) |
||
416 | +#define BCM_63268_HSSPI_BASE (0xb0001000) |
||
417 | +#define BCM_63268_UDC0_BASE (0xdeadbeef) |
||
418 | +#define BCM_63268_USBDMA_BASE (0xb000c800) |
||
419 | +#define BCM_63268_OHCI0_BASE (0xb0002600) |
||
420 | +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef) |
||
421 | +#define BCM_63268_USBH_PRIV_BASE (0xb0002700) |
||
422 | +#define BCM_63268_USBD_BASE (0xb0002400) |
||
423 | +#define BCM_63268_MPI_BASE (0xdeadbeef) |
||
424 | +#define BCM_63268_PCMCIA_BASE (0xdeadbeef) |
||
425 | +#define BCM_63268_PCIE_BASE (0xb06e0000) |
||
426 | +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef) |
||
427 | +#define BCM_63268_DSL_BASE (0xdeadbeef) |
||
428 | +#define BCM_63268_UBUS_BASE (0xdeadbeef) |
||
429 | +#define BCM_63268_ENET0_BASE (0xdeadbeef) |
||
430 | +#define BCM_63268_ENET1_BASE (0xdeadbeef) |
||
431 | +#define BCM_63268_ENETDMA_BASE (0xb000d800) |
||
432 | +#define BCM_63268_ENETDMAC_BASE (0xb000da00) |
||
433 | +#define BCM_63268_ENETDMAS_BASE (0xb000dc00) |
||
434 | +#define BCM_63268_ENETSW_BASE (0xb0700000) |
||
435 | +#define BCM_63268_EHCI0_BASE (0xb0002500) |
||
436 | +#define BCM_63268_SDRAM_BASE (0xdeadbeef) |
||
437 | +#define BCM_63268_MEMC_BASE (0xdeadbeef) |
||
438 | +#define BCM_63268_DDR_BASE (0xb0003000) |
||
439 | +#define BCM_63268_M2M_BASE (0xdeadbeef) |
||
440 | +#define BCM_63268_ATM_BASE (0xdeadbeef) |
||
441 | +#define BCM_63268_XTM_BASE (0xb0007000) |
||
442 | +#define BCM_63268_XTMDMA_BASE (0xb000b800) |
||
443 | +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef) |
||
444 | +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef) |
||
445 | +#define BCM_63268_PCM_BASE (0xb000b000) |
||
446 | +#define BCM_63268_PCMDMA_BASE (0xb000b800) |
||
447 | +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef) |
||
448 | +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef) |
||
449 | +#define BCM_63268_RNG_BASE (0xdeadbeef) |
||
450 | +#define BCM_63268_MISC_BASE (0xb0001800) |
||
451 | |||
452 | extern const unsigned long *bcm63xx_regs_base; |
||
453 | |||
454 | @@ -1041,6 +1104,73 @@ enum bcm63xx_irq { |
||
455 | #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) |
||
456 | #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) |
||
457 | |||
458 | +/* |
||
459 | + * 63268 irqs |
||
460 | + */ |
||
461 | +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) |
||
462 | +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32) |
||
463 | + |
||
464 | +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) |
||
465 | +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16) |
||
466 | +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5) |
||
467 | +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2) |
||
468 | +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23) |
||
469 | +#define BCM_63268_UDC0_IRQ 0 |
||
470 | +#define BCM_63268_ENET0_IRQ 0 |
||
471 | +#define BCM_63268_ENET1_IRQ 0 |
||
472 | +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13) |
||
473 | +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6) |
||
474 | +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) |
||
475 | +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) |
||
476 | +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11) |
||
477 | +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19) |
||
478 | +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4) |
||
479 | +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20) |
||
480 | +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5) |
||
481 | +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21) |
||
482 | +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6) |
||
483 | +#define BCM_63268_PCMCIA_IRQ 0 |
||
484 | +#define BCM_63268_ENET0_RXDMA_IRQ 0 |
||
485 | +#define BCM_63268_ENET0_TXDMA_IRQ 0 |
||
486 | +#define BCM_63268_ENET1_RXDMA_IRQ 0 |
||
487 | +#define BCM_63268_ENET1_TXDMA_IRQ 0 |
||
488 | +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8) |
||
489 | +#define BCM_63268_ATM_IRQ 0 |
||
490 | +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1) |
||
491 | +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2) |
||
492 | +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3) |
||
493 | +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4) |
||
494 | +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0) |
||
495 | +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1) |
||
496 | +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2) |
||
497 | +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3) |
||
498 | +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17) |
||
499 | +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26) |
||
500 | + |
||
501 | +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20) |
||
502 | +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3) |
||
503 | +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7) |
||
504 | +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8) |
||
505 | +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18) |
||
506 | +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13) |
||
507 | +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15) |
||
508 | +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16) |
||
509 | +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17) |
||
510 | +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18) |
||
511 | +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19) |
||
512 | +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22) |
||
513 | +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7) |
||
514 | +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24) |
||
515 | +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25) |
||
516 | +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10) |
||
517 | +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11) |
||
518 | +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0) |
||
519 | +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1) |
||
520 | +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12) |
||
521 | +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13) |
||
522 | +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14) |
||
523 | +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15) |
||
524 | + |
||
525 | extern const int *bcm63xx_irqs; |
||
526 | |||
527 | #define __GEN_CPU_IRQ_TABLE(__cpu) \ |
||
528 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |
||
529 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |
||
530 | @@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio |
||
531 | return 48; |
||
532 | case BCM6368_CPU_ID: |
||
533 | return 38; |
||
534 | + case BCM63268_CPU_ID: |
||
535 | + return 52; |
||
536 | case BCM6348_CPU_ID: |
||
537 | default: |
||
538 | return 37; |
||
539 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
||
540 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
||
541 | @@ -9,6 +9,8 @@ |
||
542 | #define PERF_REV_REG 0x0 |
||
543 | #define REV_CHIPID_SHIFT 16 |
||
544 | #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) |
||
545 | +#define REV_LONG_CHIPID_SHIFT 12 |
||
546 | +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT) |
||
547 | #define REV_VARID_SHIFT 12 |
||
548 | #define REV_VARID_MASK (0xf << REV_VARID_SHIFT) |
||
549 | #define REV_REVID_SHIFT 0 |
||
550 | @@ -211,6 +213,52 @@ |
||
551 | CKCTL_6368_NAND_EN | \ |
||
552 | CKCTL_6368_IPSEC_EN) |
||
553 | |||
554 | +#define CKCTL_63268_DISABLE_GLESS (1 << 0) |
||
555 | +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1) |
||
556 | +#define CKCTL_63268_VDSL_AFE_EN (1 << 2) |
||
557 | +#define CKCTL_63268_VDSL_EN (1 << 3) |
||
558 | +#define CKCTL_63268_MIPS_EN (1 << 4) |
||
559 | +#define CKCTL_63268_WLAN_OCP_EN (1 << 5) |
||
560 | +#define CKCTL_63268_DECT_EN (1 << 6) |
||
561 | +#define CKCTL_63268_FAP0_EN (1 << 7) |
||
562 | +#define CKCTL_63268_FAP1_EN (1 << 8) |
||
563 | +#define CKCTL_63268_SAR_EN (1 << 9) |
||
564 | +#define CKCTL_63268_ROBOSW_EN (1 << 10) |
||
565 | +#define CKCTL_63268_PCM_EN (1 << 11) |
||
566 | +#define CKCTL_63268_USBD_EN (1 << 12) |
||
567 | +#define CKCTL_63268_USBH_EN (1 << 13) |
||
568 | +#define CKCTL_63268_IPSEC_EN (1 << 14) |
||
569 | +#define CKCTL_63268_SPI_EN (1 << 15) |
||
570 | +#define CKCTL_63268_HSSPI_EN (1 << 16) |
||
571 | +#define CKCTL_63268_PCIE_EN (1 << 17) |
||
572 | +#define CKCTL_63268_PHYMIPS_EN (1 << 18) |
||
573 | +#define CKCTL_63268_GMAC_EN (1 << 19) |
||
574 | +#define CKCTL_63268_NAND_EN (1 << 20) |
||
575 | +#define CKCTL_63268_TBUS_EN (1 << 27) |
||
576 | +#define CKCTL_63268_ROBOSW250_EN (1 << 31) |
||
577 | + |
||
578 | +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \ |
||
579 | + CKCTL_63268_VDSL_AFE_EN | \ |
||
580 | + CKCTL_63268_VDSL_EN | \ |
||
581 | + CKCTL_63268_WLAN_OCP_EN | \ |
||
582 | + CKCTL_63268_DECT_EN | \ |
||
583 | + CKCTL_63268_FAP0_EN | \ |
||
584 | + CKCTL_63268_FAP1_EN | \ |
||
585 | + CKCTL_63268_SAR_EN | \ |
||
586 | + CKCTL_63268_ROBOSW_EN | \ |
||
587 | + CKCTL_63268_PCM_EN | \ |
||
588 | + CKCTL_63268_USBD_EN | \ |
||
589 | + CKCTL_63268_USBH_EN | \ |
||
590 | + CKCTL_63268_IPSEC_EN | \ |
||
591 | + CKCTL_63268_SPI_EN | \ |
||
592 | + CKCTL_63268_HSSPI_EN | \ |
||
593 | + CKCTL_63268_PCIE_EN | \ |
||
594 | + CKCTL_63268_PHYMIPS_EN | \ |
||
595 | + CKCTL_63268_GMAC_EN | \ |
||
596 | + CKCTL_63268_NAND_EN | \ |
||
597 | + CKCTL_63268_TBUS_EN | \ |
||
598 | + CKCTL_63268_ROBOSW250_EN) |
||
599 | + |
||
600 | /* System PLL Control register */ |
||
601 | #define PERF_SYS_PLL_CTL_REG 0x8 |
||
602 | #define SYS_PLL_SOFT_RESET 0x1 |
||
603 | @@ -224,6 +272,7 @@ |
||
604 | #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c) |
||
605 | #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10) |
||
606 | #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10) |
||
607 | +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20) |
||
608 | |||
609 | /* Interrupt Status register */ |
||
610 | #define PERF_IRQSTAT_3368_REG 0x10 |
||
611 | @@ -234,6 +283,7 @@ |
||
612 | #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c) |
||
613 | #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10) |
||
614 | #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10) |
||
615 | +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20) |
||
616 | |||
617 | /* External Interrupt Configuration register */ |
||
618 | #define PERF_EXTIRQ_CFG_REG_3368 0x14 |
||
619 | @@ -244,6 +294,7 @@ |
||
620 | #define PERF_EXTIRQ_CFG_REG_6358 0x14 |
||
621 | #define PERF_EXTIRQ_CFG_REG_6362 0x18 |
||
622 | #define PERF_EXTIRQ_CFG_REG_6368 0x18 |
||
623 | +#define PERF_EXTIRQ_CFG_REG_63268 0x18 |
||
624 | |||
625 | #define PERF_EXTIRQ_CFG_REG2_6358 0x1c |
||
626 | #define PERF_EXTIRQ_CFG_REG2_6368 0x1c |
||
627 | @@ -274,6 +325,7 @@ |
||
628 | #define PERF_SOFTRESET_6358_REG 0x34 |
||
629 | #define PERF_SOFTRESET_6362_REG 0x10 |
||
630 | #define PERF_SOFTRESET_6368_REG 0x10 |
||
631 | +#define PERF_SOFTRESET_63268_REG 0x10 |
||
632 | |||
633 | #define SOFTRESET_3368_SPI_MASK (1 << 0) |
||
634 | #define SOFTRESET_3368_ENET_MASK (1 << 2) |
||
635 | @@ -367,6 +419,26 @@ |
||
636 | #define SOFTRESET_6368_USBH_MASK (1 << 12) |
||
637 | #define SOFTRESET_6368_PCM_MASK (1 << 13) |
||
638 | |||
639 | +#define SOFTRESET_63268_SPI_MASK (1 << 0) |
||
640 | +#define SOFTRESET_63268_IPSEC_MASK (1 << 1) |
||
641 | +#define SOFTRESET_63268_EPHY_MASK (1 << 2) |
||
642 | +#define SOFTRESET_63268_SAR_MASK (1 << 3) |
||
643 | +#define SOFTRESET_63268_ENETSW_MASK (1 << 4) |
||
644 | +#define SOFTRESET_63268_USBS_MASK (1 << 5) |
||
645 | +#define SOFTRESET_63268_USBH_MASK (1 << 6) |
||
646 | +#define SOFTRESET_63268_PCM_MASK (1 << 7) |
||
647 | +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8) |
||
648 | +#define SOFTRESET_63268_PCIE_MASK (1 << 9) |
||
649 | +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10) |
||
650 | +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11) |
||
651 | +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12) |
||
652 | +#define SOFTRESET_63268_FAP0_MASK (1 << 13) |
||
653 | +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14) |
||
654 | +#define SOFTRESET_63268_DECT_MASK (1 << 15) |
||
655 | +#define SOFTRESET_63268_FAP1_MASK (1 << 16) |
||
656 | +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17) |
||
657 | +#define SOFTRESET_63268_GPHY_MASK (1 << 18) |
||
658 | + |
||
659 | /* MIPS PLL control register */ |
||
660 | #define PERF_MIPSPLLCTL_REG 0x34 |
||
661 | #define MIPSPLLCTL_N1_SHIFT 20 |
||
662 | @@ -1366,6 +1438,13 @@ |
||
663 | #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15) |
||
664 | #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15) |
||
665 | |||
666 | +#define MISC_STRAPBUS_63268_REG 0x14 |
||
667 | +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9) |
||
668 | +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11) |
||
669 | +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11) |
||
670 | +#define STRAPBUS_63268_FCVO_SHIFT 21 |
||
671 | +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) |
||
672 | + |
||
673 | #define MISC_STRAPBUS_6328_REG 0x240 |
||
674 | #define STRAPBUS_6328_FCVO_SHIFT 7 |
||
675 | #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) |
||
676 | --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h |
||
677 | +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h |
||
678 | @@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re |
||
679 | case BCM6328_CPU_ID: |
||
680 | case BCM6362_CPU_ID: |
||
681 | case BCM6368_CPU_ID: |
||
682 | + case BCM63268_CPU_ID: |
||
683 | if (offset >= 0xb0000000 && offset < 0xb1000000) |
||
684 | return 1; |
||
685 | break; |
||
686 | --- a/arch/mips/bcm63xx/dev-hsspi.c |
||
687 | +++ b/arch/mips/bcm63xx/dev-hsspi.c |
||
688 | @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs |
||
689 | |||
690 | int __init bcm63xx_hsspi_register(void) |
||
691 | { |
||
692 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) |
||
693 | + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268()) |
||
694 | return -ENODEV; |
||
695 | |||
696 | spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); |
||
697 | --- a/arch/mips/bcm63xx/dev-enet.c |
||
698 | +++ b/arch/mips/bcm63xx/dev-enet.c |
||
699 | @@ -176,7 +176,8 @@ static int __init register_shared(void) |
||
700 | else |
||
701 | shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; |
||
702 | |||
703 | - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) |
||
704 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() || |
||
705 | + BCMCPU_IS_63268()) |
||
706 | chan_count = 32; |
||
707 | else if (BCMCPU_IS_6345()) |
||
708 | chan_count = 8; |
||
709 | @@ -284,7 +285,8 @@ bcm63xx_enetsw_register(const struct bcm |
||
710 | { |
||
711 | int ret; |
||
712 | |||
713 | - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) |
||
714 | + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && |
||
715 | + !BCMCPU_IS_63268()) |
||
716 | return -ENODEV; |
||
717 | |||
718 | ret = register_shared(); |
||
719 | @@ -305,6 +307,8 @@ bcm63xx_enetsw_register(const struct bcm |
||
720 | enetsw_pd.num_ports = ENETSW_PORTS_6328; |
||
721 | else if (BCMCPU_IS_6362() || BCMCPU_IS_6368()) |
||
722 | enetsw_pd.num_ports = ENETSW_PORTS_6368; |
||
723 | + else if (BCMCPU_IS_63268()) |
||
724 | + enetsw_pd.num_ports = ENETSW_PORTS_63268; |
||
725 | |||
726 | enetsw_pd.dma_has_sram = true; |
||
727 | enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH; |
||
728 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h |
||
729 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h |
||
730 | @@ -66,6 +66,7 @@ struct bcm63xx_enet_platform_data { |
||
731 | #define ENETSW_MAX_PORT 8 |
||
732 | #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */ |
||
733 | #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */ |
||
734 | +#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */ |
||
735 | |||
736 | #define ENETSW_RGMII_PORT0 4 |
||
737 |