OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From d2d2489e0a4b740abd980e9d1cad952d15bc2d9e Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 30 Nov 2014 14:55:02 +0100 |
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4 | Subject: [PATCH] MIPS: BCM63XX: switch to IRQ_DOMAIN |
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5 | |||
6 | Now that we have working IRQ_DOMAIN drivers for both interrupt controllers, |
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7 | switch to using them. |
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8 | |||
9 | Signed-off-by: Jonas Gorski <jogo@openwrt.org> |
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10 | --- |
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11 | arch/mips/Kconfig | 3 + |
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12 | arch/mips/bcm63xx/irq.c | 612 +++++++++--------------------------------------- |
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13 | 2 files changed, 108 insertions(+), 507 deletions(-) |
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14 | |||
15 | --- a/arch/mips/Kconfig |
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16 | +++ b/arch/mips/Kconfig |
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17 | @@ -265,6 +265,9 @@ config BCM63XX |
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18 | select SYNC_R4K |
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19 | select DMA_NONCOHERENT |
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20 | select IRQ_MIPS_CPU |
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21 | + select BCM6345_EXT_IRQ |
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22 | + select BCM6345_PERIPH_IRQ |
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23 | + select IRQ_DOMAIN |
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24 | select SYS_SUPPORTS_32BIT_KERNEL |
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25 | select SYS_SUPPORTS_BIG_ENDIAN |
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26 | select SYS_HAS_EARLY_PRINTK |
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27 | --- a/arch/mips/bcm63xx/irq.c |
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28 | +++ b/arch/mips/bcm63xx/irq.c |
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29 | @@ -12,7 +12,9 @@ |
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30 | #include <linux/interrupt.h> |
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31 | #include <linux/module.h> |
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32 | #include <linux/irq.h> |
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33 | -#include <linux/spinlock.h> |
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34 | +#include <linux/irqchip.h> |
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35 | +#include <linux/irqchip/irq-bcm6345-ext.h> |
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36 | +#include <linux/irqchip/irq-bcm6345-periph.h> |
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37 | #include <asm/irq_cpu.h> |
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38 | #include <asm/mipsregs.h> |
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39 | #include <bcm63xx_cpu.h> |
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40 | @@ -20,544 +22,140 @@ |
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41 | #include <bcm63xx_io.h> |
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42 | #include <bcm63xx_irq.h> |
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43 | |||
44 | - |
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45 | -static DEFINE_SPINLOCK(ipic_lock); |
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46 | -static DEFINE_SPINLOCK(epic_lock); |
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47 | - |
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48 | -static u32 irq_stat_addr[2]; |
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49 | -static u32 irq_mask_addr[2]; |
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50 | -static void (*dispatch_internal)(int cpu); |
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51 | -static int is_ext_irq_cascaded; |
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52 | -static unsigned int ext_irq_count; |
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53 | -static unsigned int ext_irq_start, ext_irq_end; |
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54 | -static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2; |
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55 | -static void (*internal_irq_mask)(struct irq_data *d); |
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56 | -static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m); |
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57 | - |
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58 | - |
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59 | -static inline u32 get_ext_irq_perf_reg(int irq) |
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60 | -{ |
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61 | - if (irq < 4) |
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62 | - return ext_irq_cfg_reg1; |
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63 | - return ext_irq_cfg_reg2; |
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64 | -} |
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65 | - |
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66 | -static inline void handle_internal(int intbit) |
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67 | -{ |
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68 | - if (is_ext_irq_cascaded && |
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69 | - intbit >= ext_irq_start && intbit <= ext_irq_end) |
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70 | - do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE); |
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71 | - else |
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72 | - do_IRQ(intbit + IRQ_INTERNAL_BASE); |
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73 | -} |
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74 | - |
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75 | -static inline int enable_irq_for_cpu(int cpu, struct irq_data *d, |
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76 | - const struct cpumask *m) |
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77 | -{ |
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78 | - bool enable = cpu_online(cpu); |
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79 | - |
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80 | -#ifdef CONFIG_SMP |
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81 | - if (m) |
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82 | - enable &= cpumask_test_cpu(cpu, m); |
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83 | - else if (irqd_affinity_was_set(d)) |
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84 | - enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d)); |
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85 | -#endif |
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86 | - return enable; |
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87 | -} |
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88 | - |
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89 | -/* |
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90 | - * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not |
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91 | - * prioritize any interrupt relatively to another. the static counter |
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92 | - * will resume the loop where it ended the last time we left this |
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93 | - * function. |
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94 | - */ |
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95 | - |
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96 | -#define BUILD_IPIC_INTERNAL(width) \ |
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97 | -void __dispatch_internal_##width(int cpu) \ |
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98 | -{ \ |
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99 | - u32 pending[width / 32]; \ |
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100 | - unsigned int src, tgt; \ |
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101 | - bool irqs_pending = false; \ |
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102 | - static unsigned int i[2]; \ |
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103 | - unsigned int *next = &i[cpu]; \ |
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104 | - unsigned long flags; \ |
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105 | - \ |
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106 | - /* read registers in reverse order */ \ |
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107 | - spin_lock_irqsave(&ipic_lock, flags); \ |
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108 | - for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ |
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109 | - u32 val; \ |
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110 | - \ |
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111 | - val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ |
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112 | - val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ |
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113 | - pending[--tgt] = val; \ |
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114 | - \ |
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115 | - if (val) \ |
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116 | - irqs_pending = true; \ |
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117 | - } \ |
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118 | - spin_unlock_irqrestore(&ipic_lock, flags); \ |
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119 | - \ |
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120 | - if (!irqs_pending) \ |
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121 | - return; \ |
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122 | - \ |
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123 | - while (1) { \ |
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124 | - unsigned int to_call = *next; \ |
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125 | - \ |
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126 | - *next = (*next + 1) & (width - 1); \ |
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127 | - if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ |
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128 | - handle_internal(to_call); \ |
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129 | - break; \ |
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130 | - } \ |
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131 | - } \ |
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132 | -} \ |
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133 | - \ |
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134 | -static void __internal_irq_mask_##width(struct irq_data *d) \ |
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135 | -{ \ |
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136 | - u32 val; \ |
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137 | - unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ |
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138 | - unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
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139 | - unsigned bit = irq & 0x1f; \ |
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140 | - unsigned long flags; \ |
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141 | - int cpu; \ |
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142 | - \ |
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143 | - spin_lock_irqsave(&ipic_lock, flags); \ |
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144 | - for_each_present_cpu(cpu) { \ |
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145 | - if (!irq_mask_addr[cpu]) \ |
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146 | - break; \ |
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147 | - \ |
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148 | - val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ |
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149 | - val &= ~(1 << bit); \ |
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150 | - bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ |
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151 | - } \ |
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152 | - spin_unlock_irqrestore(&ipic_lock, flags); \ |
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153 | -} \ |
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154 | - \ |
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155 | -static void __internal_irq_unmask_##width(struct irq_data *d, \ |
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156 | - const struct cpumask *m) \ |
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157 | -{ \ |
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158 | - u32 val; \ |
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159 | - unsigned irq = d->irq - IRQ_INTERNAL_BASE; \ |
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160 | - unsigned reg = (irq / 32) ^ (width/32 - 1); \ |
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161 | - unsigned bit = irq & 0x1f; \ |
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162 | - unsigned long flags; \ |
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163 | - int cpu; \ |
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164 | - \ |
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165 | - spin_lock_irqsave(&ipic_lock, flags); \ |
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166 | - for_each_present_cpu(cpu) { \ |
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167 | - if (!irq_mask_addr[cpu]) \ |
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168 | - break; \ |
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169 | - \ |
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170 | - val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\ |
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171 | - if (enable_irq_for_cpu(cpu, d, m)) \ |
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172 | - val |= (1 << bit); \ |
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173 | - else \ |
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174 | - val &= ~(1 << bit); \ |
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175 | - bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\ |
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176 | - } \ |
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177 | - spin_unlock_irqrestore(&ipic_lock, flags); \ |
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178 | -} |
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179 | - |
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180 | -BUILD_IPIC_INTERNAL(32); |
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181 | -BUILD_IPIC_INTERNAL(64); |
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182 | - |
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183 | -asmlinkage void plat_irq_dispatch(void) |
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184 | -{ |
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185 | - u32 cause; |
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186 | - |
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187 | - do { |
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188 | - cause = read_c0_cause() & read_c0_status() & ST0_IM; |
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189 | - |
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190 | - if (!cause) |
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191 | - break; |
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192 | - |
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193 | - if (cause & CAUSEF_IP7) |
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194 | - do_IRQ(7); |
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195 | - if (cause & CAUSEF_IP0) |
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196 | - do_IRQ(0); |
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197 | - if (cause & CAUSEF_IP1) |
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198 | - do_IRQ(1); |
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199 | - if (cause & CAUSEF_IP2) |
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200 | - dispatch_internal(0); |
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201 | - if (is_ext_irq_cascaded) { |
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202 | - if (cause & CAUSEF_IP3) |
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203 | - dispatch_internal(1); |
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204 | - } else { |
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205 | - if (cause & CAUSEF_IP3) |
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206 | - do_IRQ(IRQ_EXT_0); |
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207 | - if (cause & CAUSEF_IP4) |
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208 | - do_IRQ(IRQ_EXT_1); |
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209 | - if (cause & CAUSEF_IP5) |
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210 | - do_IRQ(IRQ_EXT_2); |
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211 | - if (cause & CAUSEF_IP6) |
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212 | - do_IRQ(IRQ_EXT_3); |
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213 | - } |
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214 | - } while (1); |
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215 | -} |
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216 | - |
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217 | -/* |
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218 | - * internal IRQs operations: only mask/unmask on PERF irq mask |
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219 | - * register. |
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220 | - */ |
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221 | -static void bcm63xx_internal_irq_mask(struct irq_data *d) |
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222 | -{ |
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223 | - internal_irq_mask(d); |
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224 | -} |
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225 | - |
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226 | -static void bcm63xx_internal_irq_unmask(struct irq_data *d) |
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227 | -{ |
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228 | - internal_irq_unmask(d, NULL); |
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229 | -} |
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230 | - |
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231 | -/* |
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232 | - * external IRQs operations: mask/unmask and clear on PERF external |
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233 | - * irq control register. |
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234 | - */ |
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235 | -static void bcm63xx_external_irq_mask(struct irq_data *d) |
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236 | -{ |
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237 | - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
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238 | - u32 reg, regaddr; |
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239 | - unsigned long flags; |
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240 | - |
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241 | - regaddr = get_ext_irq_perf_reg(irq); |
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242 | - spin_lock_irqsave(&epic_lock, flags); |
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243 | - reg = bcm_perf_readl(regaddr); |
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244 | - |
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245 | - if (BCMCPU_IS_6348()) |
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246 | - reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4); |
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247 | - else |
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248 | - reg &= ~EXTIRQ_CFG_MASK(irq % 4); |
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249 | - |
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250 | - bcm_perf_writel(reg, regaddr); |
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251 | - spin_unlock_irqrestore(&epic_lock, flags); |
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252 | - |
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253 | - if (is_ext_irq_cascaded) |
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254 | - internal_irq_mask(irq_get_irq_data(irq + ext_irq_start)); |
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255 | -} |
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256 | - |
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257 | -static void bcm63xx_external_irq_unmask(struct irq_data *d) |
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258 | -{ |
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259 | - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
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260 | - u32 reg, regaddr; |
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261 | - unsigned long flags; |
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262 | - |
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263 | - regaddr = get_ext_irq_perf_reg(irq); |
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264 | - spin_lock_irqsave(&epic_lock, flags); |
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265 | - reg = bcm_perf_readl(regaddr); |
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266 | - |
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267 | - if (BCMCPU_IS_6348()) |
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268 | - reg |= EXTIRQ_CFG_MASK_6348(irq % 4); |
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269 | - else |
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270 | - reg |= EXTIRQ_CFG_MASK(irq % 4); |
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271 | - |
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272 | - bcm_perf_writel(reg, regaddr); |
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273 | - spin_unlock_irqrestore(&epic_lock, flags); |
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274 | - |
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275 | - if (is_ext_irq_cascaded) |
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276 | - internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start), |
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277 | - NULL); |
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278 | -} |
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279 | - |
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280 | -static void bcm63xx_external_irq_clear(struct irq_data *d) |
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281 | -{ |
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282 | - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
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283 | - u32 reg, regaddr; |
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284 | - unsigned long flags; |
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285 | - |
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286 | - regaddr = get_ext_irq_perf_reg(irq); |
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287 | - spin_lock_irqsave(&epic_lock, flags); |
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288 | - reg = bcm_perf_readl(regaddr); |
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289 | - |
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290 | - if (BCMCPU_IS_6348()) |
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291 | - reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4); |
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292 | - else |
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293 | - reg |= EXTIRQ_CFG_CLEAR(irq % 4); |
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294 | - |
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295 | - bcm_perf_writel(reg, regaddr); |
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296 | - spin_unlock_irqrestore(&epic_lock, flags); |
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297 | -} |
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298 | - |
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299 | -static int bcm63xx_external_irq_set_type(struct irq_data *d, |
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300 | - unsigned int flow_type) |
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301 | -{ |
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302 | - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE; |
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303 | - u32 reg, regaddr; |
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304 | - int levelsense, sense, bothedge; |
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305 | - unsigned long flags; |
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306 | - |
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307 | - flow_type &= IRQ_TYPE_SENSE_MASK; |
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308 | - |
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309 | - if (flow_type == IRQ_TYPE_NONE) |
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310 | - flow_type = IRQ_TYPE_LEVEL_LOW; |
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311 | - |
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312 | - levelsense = sense = bothedge = 0; |
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313 | - switch (flow_type) { |
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314 | - case IRQ_TYPE_EDGE_BOTH: |
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315 | - bothedge = 1; |
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316 | - break; |
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317 | - |
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318 | - case IRQ_TYPE_EDGE_RISING: |
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319 | - sense = 1; |
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320 | - break; |
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321 | - |
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322 | - case IRQ_TYPE_EDGE_FALLING: |
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323 | - break; |
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324 | - |
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325 | - case IRQ_TYPE_LEVEL_HIGH: |
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326 | - levelsense = 1; |
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327 | - sense = 1; |
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328 | - break; |
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329 | - |
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330 | - case IRQ_TYPE_LEVEL_LOW: |
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331 | - levelsense = 1; |
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332 | - break; |
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333 | - |
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334 | - default: |
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335 | - pr_err("bogus flow type combination given !\n"); |
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336 | - return -EINVAL; |
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337 | - } |
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338 | - |
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339 | - regaddr = get_ext_irq_perf_reg(irq); |
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340 | - spin_lock_irqsave(&epic_lock, flags); |
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341 | - reg = bcm_perf_readl(regaddr); |
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342 | - irq %= 4; |
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343 | - |
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344 | - switch (bcm63xx_get_cpu_id()) { |
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345 | - case BCM6348_CPU_ID: |
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346 | - if (levelsense) |
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347 | - reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq); |
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348 | - else |
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349 | - reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq); |
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350 | - if (sense) |
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351 | - reg |= EXTIRQ_CFG_SENSE_6348(irq); |
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352 | - else |
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353 | - reg &= ~EXTIRQ_CFG_SENSE_6348(irq); |
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354 | - if (bothedge) |
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355 | - reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq); |
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356 | - else |
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357 | - reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); |
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358 | - break; |
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359 | - |
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360 | - case BCM3368_CPU_ID: |
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361 | - case BCM6328_CPU_ID: |
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362 | - case BCM6338_CPU_ID: |
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363 | - case BCM6345_CPU_ID: |
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364 | - case BCM6358_CPU_ID: |
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365 | - case BCM6362_CPU_ID: |
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366 | - case BCM6368_CPU_ID: |
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367 | - if (levelsense) |
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368 | - reg |= EXTIRQ_CFG_LEVELSENSE(irq); |
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369 | - else |
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370 | - reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); |
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371 | - if (sense) |
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372 | - reg |= EXTIRQ_CFG_SENSE(irq); |
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373 | - else |
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374 | - reg &= ~EXTIRQ_CFG_SENSE(irq); |
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375 | - if (bothedge) |
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376 | - reg |= EXTIRQ_CFG_BOTHEDGE(irq); |
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377 | - else |
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378 | - reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); |
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379 | - break; |
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380 | - default: |
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381 | - BUG(); |
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382 | - } |
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383 | - |
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384 | - bcm_perf_writel(reg, regaddr); |
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385 | - spin_unlock_irqrestore(&epic_lock, flags); |
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386 | - |
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387 | - irqd_set_trigger_type(d, flow_type); |
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388 | - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
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389 | - irq_set_handler_locked(d, handle_level_irq); |
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390 | - else |
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391 | - irq_set_handler_locked(d, handle_edge_irq); |
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392 | - |
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393 | - return IRQ_SET_MASK_OK_NOCOPY; |
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394 | -} |
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395 | - |
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396 | -#ifdef CONFIG_SMP |
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397 | -static int bcm63xx_internal_set_affinity(struct irq_data *data, |
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398 | - const struct cpumask *dest, |
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399 | - bool force) |
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400 | -{ |
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401 | - if (!irqd_irq_disabled(data)) |
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402 | - internal_irq_unmask(data, dest); |
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403 | - |
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404 | - return 0; |
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405 | -} |
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406 | -#endif |
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407 | - |
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408 | -static struct irq_chip bcm63xx_internal_irq_chip = { |
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409 | - .name = "bcm63xx_ipic", |
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410 | - .irq_mask = bcm63xx_internal_irq_mask, |
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411 | - .irq_unmask = bcm63xx_internal_irq_unmask, |
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412 | -}; |
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413 | - |
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414 | -static struct irq_chip bcm63xx_external_irq_chip = { |
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415 | - .name = "bcm63xx_epic", |
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416 | - .irq_ack = bcm63xx_external_irq_clear, |
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417 | - |
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418 | - .irq_mask = bcm63xx_external_irq_mask, |
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419 | - .irq_unmask = bcm63xx_external_irq_unmask, |
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420 | - |
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421 | - .irq_set_type = bcm63xx_external_irq_set_type, |
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422 | -}; |
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423 | - |
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424 | -static struct irqaction cpu_ip2_cascade_action = { |
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425 | - .handler = no_action, |
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426 | - .name = "cascade_ip2", |
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427 | - .flags = IRQF_NO_THREAD, |
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428 | -}; |
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429 | - |
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430 | -#ifdef CONFIG_SMP |
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431 | -static struct irqaction cpu_ip3_cascade_action = { |
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432 | - .handler = no_action, |
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433 | - .name = "cascade_ip3", |
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434 | - .flags = IRQF_NO_THREAD, |
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435 | -}; |
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436 | -#endif |
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437 | - |
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438 | -static struct irqaction cpu_ext_cascade_action = { |
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439 | - .handler = no_action, |
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440 | - .name = "cascade_extirq", |
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441 | - .flags = IRQF_NO_THREAD, |
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442 | -}; |
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443 | - |
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444 | -static void bcm63xx_init_irq(void) |
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445 | +void __init arch_init_irq(void) |
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446 | { |
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447 | - int irq_bits; |
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448 | - |
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449 | - irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF); |
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450 | - irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF); |
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451 | - irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF); |
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452 | - irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF); |
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453 | + void __iomem *periph_bases[2]; |
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454 | + void __iomem *ext_intc_bases[2]; |
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455 | + int periph_irq_count, periph_width, ext_irq_count, ext_shift; |
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456 | + int periph_irqs[2] = { 2, 3 }; |
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457 | + int ext_irqs[6]; |
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458 | + |
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459 | + periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); |
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460 | + periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); |
||
461 | + ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); |
||
462 | + ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF); |
||
463 | |||
464 | switch (bcm63xx_get_cpu_id()) { |
||
465 | case BCM3368_CPU_ID: |
||
466 | - irq_stat_addr[0] += PERF_IRQSTAT_3368_REG; |
||
467 | - irq_mask_addr[0] += PERF_IRQMASK_3368_REG; |
||
468 | - irq_stat_addr[1] = 0; |
||
469 | - irq_mask_addr[1] = 0; |
||
470 | - irq_bits = 32; |
||
471 | - ext_irq_count = 4; |
||
472 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368; |
||
473 | + periph_bases[0] += PERF_IRQMASK_3368_REG; |
||
474 | + periph_irq_count = 1; |
||
475 | + periph_width = 1; |
||
476 | + |
||
477 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368; |
||
478 | + ext_irq_count = 4; |
||
479 | + ext_irqs[0] = BCM_3368_EXT_IRQ0; |
||
480 | + ext_irqs[1] = BCM_3368_EXT_IRQ1; |
||
481 | + ext_irqs[2] = BCM_3368_EXT_IRQ2; |
||
482 | + ext_irqs[3] = BCM_3368_EXT_IRQ3; |
||
483 | + ext_shift = 4; |
||
484 | break; |
||
485 | case BCM6328_CPU_ID: |
||
486 | - irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0); |
||
487 | - irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0); |
||
488 | - irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1); |
||
489 | - irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1); |
||
490 | - irq_bits = 64; |
||
491 | - ext_irq_count = 4; |
||
492 | - is_ext_irq_cascaded = 1; |
||
493 | - ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
||
494 | - ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
||
495 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; |
||
496 | + periph_bases[0] += PERF_IRQMASK_6328_REG(0); |
||
497 | + periph_bases[1] += PERF_IRQMASK_6328_REG(1); |
||
498 | + periph_irq_count = 2; |
||
499 | + periph_width = 2; |
||
500 | + |
||
501 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328; |
||
502 | + ext_irq_count = 4; |
||
503 | + ext_irqs[0] = BCM_6328_EXT_IRQ0; |
||
504 | + ext_irqs[1] = BCM_6328_EXT_IRQ1; |
||
505 | + ext_irqs[2] = BCM_6328_EXT_IRQ2; |
||
506 | + ext_irqs[3] = BCM_6328_EXT_IRQ3; |
||
507 | + ext_shift = 4; |
||
508 | break; |
||
509 | case BCM6338_CPU_ID: |
||
510 | - irq_stat_addr[0] += PERF_IRQSTAT_6338_REG; |
||
511 | - irq_mask_addr[0] += PERF_IRQMASK_6338_REG; |
||
512 | - irq_stat_addr[1] = 0; |
||
513 | - irq_mask_addr[1] = 0; |
||
514 | - irq_bits = 32; |
||
515 | - ext_irq_count = 4; |
||
516 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338; |
||
517 | + periph_bases[0] += PERF_IRQMASK_6338_REG; |
||
518 | + periph_irq_count = 1; |
||
519 | + periph_width = 1; |
||
520 | + |
||
521 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338; |
||
522 | + ext_irq_count = 4; |
||
523 | + ext_irqs[0] = 3; |
||
524 | + ext_irqs[1] = 4; |
||
525 | + ext_irqs[2] = 5; |
||
526 | + ext_irqs[3] = 6; |
||
527 | + ext_shift = 4; |
||
528 | break; |
||
529 | case BCM6345_CPU_ID: |
||
530 | - irq_stat_addr[0] += PERF_IRQSTAT_6345_REG; |
||
531 | - irq_mask_addr[0] += PERF_IRQMASK_6345_REG; |
||
532 | - irq_stat_addr[1] = 0; |
||
533 | - irq_mask_addr[1] = 0; |
||
534 | - irq_bits = 32; |
||
535 | - ext_irq_count = 4; |
||
536 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345; |
||
537 | + periph_bases[0] += PERF_IRQMASK_6345_REG; |
||
538 | + periph_irq_count = 1; |
||
539 | + periph_width = 1; |
||
540 | + |
||
541 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345; |
||
542 | + ext_irq_count = 4; |
||
543 | + ext_irqs[0] = 3; |
||
544 | + ext_irqs[1] = 4; |
||
545 | + ext_irqs[2] = 5; |
||
546 | + ext_irqs[3] = 6; |
||
547 | + ext_shift = 4; |
||
548 | break; |
||
549 | case BCM6348_CPU_ID: |
||
550 | - irq_stat_addr[0] += PERF_IRQSTAT_6348_REG; |
||
551 | - irq_mask_addr[0] += PERF_IRQMASK_6348_REG; |
||
552 | - irq_stat_addr[1] = 0; |
||
553 | - irq_mask_addr[1] = 0; |
||
554 | - irq_bits = 32; |
||
555 | - ext_irq_count = 4; |
||
556 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348; |
||
557 | + periph_bases[0] += PERF_IRQMASK_6348_REG; |
||
558 | + periph_irq_count = 1; |
||
559 | + periph_width = 1; |
||
560 | + |
||
561 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348; |
||
562 | + ext_irq_count = 4; |
||
563 | + ext_irqs[0] = 3; |
||
564 | + ext_irqs[1] = 4; |
||
565 | + ext_irqs[2] = 5; |
||
566 | + ext_irqs[3] = 6; |
||
567 | + ext_shift = 5; |
||
568 | break; |
||
569 | case BCM6358_CPU_ID: |
||
570 | - irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0); |
||
571 | - irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0); |
||
572 | - irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1); |
||
573 | - irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1); |
||
574 | - irq_bits = 32; |
||
575 | - ext_irq_count = 4; |
||
576 | - is_ext_irq_cascaded = 1; |
||
577 | - ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
||
578 | - ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
||
579 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; |
||
580 | + periph_bases[0] += PERF_IRQMASK_6358_REG(0); |
||
581 | + periph_bases[1] += PERF_IRQMASK_6358_REG(1); |
||
582 | + periph_irq_count = 2; |
||
583 | + periph_width = 1; |
||
584 | + |
||
585 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358; |
||
586 | + ext_irq_count = 4; |
||
587 | + ext_irqs[0] = BCM_6358_EXT_IRQ0; |
||
588 | + ext_irqs[1] = BCM_6358_EXT_IRQ1; |
||
589 | + ext_irqs[2] = BCM_6358_EXT_IRQ2; |
||
590 | + ext_irqs[3] = BCM_6358_EXT_IRQ3; |
||
591 | + ext_shift = 4; |
||
592 | break; |
||
593 | case BCM6362_CPU_ID: |
||
594 | - irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0); |
||
595 | - irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0); |
||
596 | - irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1); |
||
597 | - irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1); |
||
598 | - irq_bits = 64; |
||
599 | - ext_irq_count = 4; |
||
600 | - is_ext_irq_cascaded = 1; |
||
601 | - ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
||
602 | - ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE; |
||
603 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362; |
||
604 | + periph_bases[0] += PERF_IRQMASK_6362_REG(0); |
||
605 | + periph_bases[1] += PERF_IRQMASK_6362_REG(1); |
||
606 | + periph_irq_count = 2; |
||
607 | + periph_width = 2; |
||
608 | + |
||
609 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362; |
||
610 | + ext_irq_count = 4; |
||
611 | + ext_irqs[0] = BCM_6362_EXT_IRQ0; |
||
612 | + ext_irqs[1] = BCM_6362_EXT_IRQ1; |
||
613 | + ext_irqs[2] = BCM_6362_EXT_IRQ2; |
||
614 | + ext_irqs[3] = BCM_6362_EXT_IRQ3; |
||
615 | + ext_shift = 4; |
||
616 | break; |
||
617 | case BCM6368_CPU_ID: |
||
618 | - irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0); |
||
619 | - irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0); |
||
620 | - irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1); |
||
621 | - irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1); |
||
622 | - irq_bits = 64; |
||
623 | + periph_bases[0] += PERF_IRQMASK_6368_REG(0); |
||
624 | + periph_bases[1] += PERF_IRQMASK_6368_REG(1); |
||
625 | + periph_irq_count = 2; |
||
626 | + periph_width = 2; |
||
627 | + |
||
628 | + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368; |
||
629 | + ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368; |
||
630 | ext_irq_count = 6; |
||
631 | - is_ext_irq_cascaded = 1; |
||
632 | - ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE; |
||
633 | - ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE; |
||
634 | - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368; |
||
635 | - ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368; |
||
636 | + ext_irqs[0] = BCM_6368_EXT_IRQ0; |
||
637 | + ext_irqs[1] = BCM_6368_EXT_IRQ1; |
||
638 | + ext_irqs[2] = BCM_6368_EXT_IRQ2; |
||
639 | + ext_irqs[3] = BCM_6368_EXT_IRQ3; |
||
640 | + ext_irqs[4] = BCM_6368_EXT_IRQ4; |
||
641 | + ext_irqs[5] = BCM_6368_EXT_IRQ5; |
||
642 | + ext_shift = 4; |
||
643 | break; |
||
644 | default: |
||
645 | BUG(); |
||
646 | } |
||
647 | |||
648 | - if (irq_bits == 32) { |
||
649 | - dispatch_internal = __dispatch_internal_32; |
||
650 | - internal_irq_mask = __internal_irq_mask_32; |
||
651 | - internal_irq_unmask = __internal_irq_unmask_32; |
||
652 | - } else { |
||
653 | - dispatch_internal = __dispatch_internal_64; |
||
654 | - internal_irq_mask = __internal_irq_mask_64; |
||
655 | - internal_irq_unmask = __internal_irq_unmask_64; |
||
656 | - } |
||
657 | -} |
||
658 | - |
||
659 | -void __init arch_init_irq(void) |
||
660 | -{ |
||
661 | - int i; |
||
662 | - |
||
663 | - bcm63xx_init_irq(); |
||
664 | mips_cpu_irq_init(); |
||
665 | - for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) |
||
666 | - irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, |
||
667 | - handle_level_irq); |
||
668 | - |
||
669 | - for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i) |
||
670 | - irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, |
||
671 | - handle_edge_irq); |
||
672 | - |
||
673 | - if (!is_ext_irq_cascaded) { |
||
674 | - for (i = 3; i < 3 + ext_irq_count; ++i) |
||
675 | - setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action); |
||
676 | - } |
||
677 | - |
||
678 | - setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action); |
||
679 | -#ifdef CONFIG_SMP |
||
680 | - if (is_ext_irq_cascaded) { |
||
681 | - setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action); |
||
682 | - bcm63xx_internal_irq_chip.irq_set_affinity = |
||
683 | - bcm63xx_internal_set_affinity; |
||
684 | - |
||
685 | - cpumask_clear(irq_default_affinity); |
||
686 | - cpumask_set_cpu(smp_processor_id(), irq_default_affinity); |
||
687 | - } |
||
688 | -#endif |
||
689 | + bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases, |
||
690 | + periph_width); |
||
691 | + bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift); |
||
692 | + if (ext_irq_count > 4) |
||
693 | + bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1], |
||
694 | + ext_shift); |
||
695 | } |