OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From 90be3cb4f1a45b8be4a4ec264cd66c2f8e893fcb Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Fri, 24 Jun 2016 22:18:25 +0200 |
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4 | Subject: [PATCH 11/16] pinctrl: add a pincontrol driver for BCM6368 |
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5 | |||
6 | Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 |
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7 | GPIOs onto alternative functions. Not all are documented. |
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8 | |||
9 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
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10 | --- |
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11 | drivers/pinctrl/bcm63xx/Kconfig | 15 + |
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12 | drivers/pinctrl/bcm63xx/Makefile | 1 + |
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13 | drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c | 573 ++++++++++++++++++++++++++++++ |
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14 | 3 files changed, 589 insertions(+) |
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15 | create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c |
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16 | |||
17 | --- a/drivers/pinctrl/bcm63xx/Kconfig |
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18 | +++ b/drivers/pinctrl/bcm63xx/Kconfig |
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19 | @@ -30,3 +30,18 @@ config PINCTRL_BCM6362 |
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20 | select PINCONF |
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21 | select PINCTRL_BCM63XX |
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22 | select GENERIC_PINCONF |
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23 | + |
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24 | +config PINCTRL_BCM6368 |
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25 | + bool "BCM6368 pincontrol driver" if COMPILE_TEST |
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26 | + select PINMUX |
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27 | + select PINCONF |
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28 | + select PINCTRL_BCM63XX |
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29 | + select GENERIC_PINCONF |
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30 | + select MFD_SYSCON |
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31 | + |
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32 | +config PINCTRL_BCM63268 |
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33 | + bool "BCM63268 pincontrol driver" if COMPILE_TEST |
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34 | + select PINMUX |
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35 | + select PINCONF |
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36 | + select PINCTRL_BCM63XX |
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37 | + select GENERIC_PINCONF |
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38 | --- a/drivers/pinctrl/bcm63xx/Makefile |
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39 | +++ b/drivers/pinctrl/bcm63xx/Makefile |
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40 | @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl |
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41 | obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o |
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42 | obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o |
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43 | obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o |
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44 | +obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o |
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45 | --- /dev/null |
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46 | +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c |
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47 | @@ -0,0 +1,573 @@ |
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48 | +/* |
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49 | + * This file is subject to the terms and conditions of the GNU General Public |
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50 | + * License. See the file "COPYING" in the main directory of this archive |
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51 | + * for more details. |
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52 | + * |
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53 | + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com> |
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54 | + */ |
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55 | + |
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56 | +#include <linux/bitops.h> |
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57 | +#include <linux/kernel.h> |
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58 | +#include <linux/gpio.h> |
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59 | +#include <linux/mfd/syscon.h> |
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60 | +#include <linux/of.h> |
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61 | +#include <linux/of_address.h> |
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62 | +#include <linux/of_gpio.h> |
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63 | +#include <linux/pinctrl/pinconf.h> |
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64 | +#include <linux/pinctrl/pinconf-generic.h> |
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65 | +#include <linux/pinctrl/pinmux.h> |
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66 | +#include <linux/pinctrl/machine.h> |
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67 | +#include <linux/platform_device.h> |
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68 | +#include <linux/regmap.h> |
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69 | +#include <linux/slab.h> |
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70 | +#include <linux/spinlock.h> |
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71 | + |
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72 | +#include "../core.h" |
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73 | +#include "../pinctrl-utils.h" |
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74 | + |
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75 | +#include "pinctrl-bcm63xx.h" |
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76 | + |
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77 | +#define BCM6368_NGPIO 38 |
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78 | + |
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79 | +#define BCM6368_BASEMODE_MASK 0x7 |
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80 | +#define BCM6368_BASEMODE_GPIO 0x0 |
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81 | +#define BCM6368_BASEMODE_UART1 0x1 |
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82 | + |
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83 | +struct bcm6368_pingroup { |
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84 | + const char *name; |
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85 | + const unsigned * const pins; |
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86 | + const unsigned num_pins; |
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87 | +}; |
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88 | + |
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89 | +struct bcm6368_function { |
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90 | + const char *name; |
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91 | + const char * const *groups; |
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92 | + const unsigned num_groups; |
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93 | + |
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94 | + unsigned dir_out:16; |
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95 | + unsigned basemode:3; |
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96 | +}; |
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97 | + |
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98 | +struct bcm6368_pinctrl { |
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99 | + struct pinctrl_dev *pctldev; |
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100 | + struct pinctrl_desc desc; |
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101 | + |
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102 | + void __iomem *mode; |
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103 | + struct regmap_field *overlay; |
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104 | + |
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105 | + /* register access lock */ |
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106 | + spinlock_t lock; |
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107 | + |
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108 | + struct gpio_chip gpio[2]; |
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109 | +}; |
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110 | + |
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111 | +#define BCM6368_BASEMODE_PIN(a, b) \ |
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112 | + { \ |
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113 | + .number = a, \ |
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114 | + .name = b, \ |
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115 | + .drv_data = (void *)true \ |
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116 | + } |
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117 | + |
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118 | +static const struct pinctrl_pin_desc bcm6368_pins[] = { |
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119 | + PINCTRL_PIN(0, "gpio0"), |
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120 | + PINCTRL_PIN(1, "gpio1"), |
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121 | + PINCTRL_PIN(2, "gpio2"), |
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122 | + PINCTRL_PIN(3, "gpio3"), |
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123 | + PINCTRL_PIN(4, "gpio4"), |
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124 | + PINCTRL_PIN(5, "gpio5"), |
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125 | + PINCTRL_PIN(6, "gpio6"), |
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126 | + PINCTRL_PIN(7, "gpio7"), |
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127 | + PINCTRL_PIN(8, "gpio8"), |
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128 | + PINCTRL_PIN(9, "gpio9"), |
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129 | + PINCTRL_PIN(10, "gpio10"), |
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130 | + PINCTRL_PIN(11, "gpio11"), |
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131 | + PINCTRL_PIN(12, "gpio12"), |
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132 | + PINCTRL_PIN(13, "gpio13"), |
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133 | + PINCTRL_PIN(14, "gpio14"), |
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134 | + PINCTRL_PIN(15, "gpio15"), |
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135 | + PINCTRL_PIN(16, "gpio16"), |
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136 | + PINCTRL_PIN(17, "gpio17"), |
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137 | + PINCTRL_PIN(18, "gpio18"), |
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138 | + PINCTRL_PIN(19, "gpio19"), |
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139 | + PINCTRL_PIN(20, "gpio20"), |
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140 | + PINCTRL_PIN(21, "gpio21"), |
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141 | + PINCTRL_PIN(22, "gpio22"), |
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142 | + PINCTRL_PIN(23, "gpio23"), |
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143 | + PINCTRL_PIN(24, "gpio24"), |
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144 | + PINCTRL_PIN(25, "gpio25"), |
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145 | + PINCTRL_PIN(26, "gpio26"), |
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146 | + PINCTRL_PIN(27, "gpio27"), |
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147 | + PINCTRL_PIN(28, "gpio28"), |
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148 | + PINCTRL_PIN(29, "gpio29"), |
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149 | + BCM6368_BASEMODE_PIN(30, "gpio30"), |
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150 | + BCM6368_BASEMODE_PIN(31, "gpio31"), |
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151 | + BCM6368_BASEMODE_PIN(32, "gpio32"), |
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152 | + BCM6368_BASEMODE_PIN(33, "gpio33"), |
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153 | + PINCTRL_PIN(34, "gpio34"), |
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154 | + PINCTRL_PIN(35, "gpio35"), |
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155 | + PINCTRL_PIN(36, "gpio36"), |
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156 | + PINCTRL_PIN(37, "gpio37"), |
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157 | +}; |
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158 | + |
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159 | +static unsigned gpio0_pins[] = { 0 }; |
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160 | +static unsigned gpio1_pins[] = { 1 }; |
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161 | +static unsigned gpio2_pins[] = { 2 }; |
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162 | +static unsigned gpio3_pins[] = { 3 }; |
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163 | +static unsigned gpio4_pins[] = { 4 }; |
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164 | +static unsigned gpio5_pins[] = { 5 }; |
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165 | +static unsigned gpio6_pins[] = { 6 }; |
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166 | +static unsigned gpio7_pins[] = { 7 }; |
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167 | +static unsigned gpio8_pins[] = { 8 }; |
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168 | +static unsigned gpio9_pins[] = { 9 }; |
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169 | +static unsigned gpio10_pins[] = { 10 }; |
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170 | +static unsigned gpio11_pins[] = { 11 }; |
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171 | +static unsigned gpio12_pins[] = { 12 }; |
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172 | +static unsigned gpio13_pins[] = { 13 }; |
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173 | +static unsigned gpio14_pins[] = { 14 }; |
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174 | +static unsigned gpio15_pins[] = { 15 }; |
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175 | +static unsigned gpio16_pins[] = { 16 }; |
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176 | +static unsigned gpio17_pins[] = { 17 }; |
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177 | +static unsigned gpio18_pins[] = { 18 }; |
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178 | +static unsigned gpio19_pins[] = { 19 }; |
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179 | +static unsigned gpio20_pins[] = { 20 }; |
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180 | +static unsigned gpio21_pins[] = { 21 }; |
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181 | +static unsigned gpio22_pins[] = { 22 }; |
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182 | +static unsigned gpio23_pins[] = { 23 }; |
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183 | +static unsigned gpio24_pins[] = { 24 }; |
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184 | +static unsigned gpio25_pins[] = { 25 }; |
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185 | +static unsigned gpio26_pins[] = { 26 }; |
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186 | +static unsigned gpio27_pins[] = { 27 }; |
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187 | +static unsigned gpio28_pins[] = { 28 }; |
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188 | +static unsigned gpio29_pins[] = { 29 }; |
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189 | +static unsigned gpio30_pins[] = { 30 }; |
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190 | +static unsigned gpio31_pins[] = { 31 }; |
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191 | +static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 }; |
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192 | + |
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193 | +#define BCM6368_GROUP(n) \ |
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194 | + { \ |
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195 | + .name = #n, \ |
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196 | + .pins = n##_pins, \ |
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197 | + .num_pins = ARRAY_SIZE(n##_pins), \ |
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198 | + } |
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199 | + |
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200 | +static struct bcm6368_pingroup bcm6368_groups[] = { |
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201 | + BCM6368_GROUP(gpio0), |
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202 | + BCM6368_GROUP(gpio1), |
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203 | + BCM6368_GROUP(gpio2), |
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204 | + BCM6368_GROUP(gpio3), |
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205 | + BCM6368_GROUP(gpio4), |
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206 | + BCM6368_GROUP(gpio5), |
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207 | + BCM6368_GROUP(gpio6), |
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208 | + BCM6368_GROUP(gpio7), |
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209 | + BCM6368_GROUP(gpio8), |
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210 | + BCM6368_GROUP(gpio9), |
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211 | + BCM6368_GROUP(gpio10), |
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212 | + BCM6368_GROUP(gpio11), |
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213 | + BCM6368_GROUP(gpio12), |
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214 | + BCM6368_GROUP(gpio13), |
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215 | + BCM6368_GROUP(gpio14), |
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216 | + BCM6368_GROUP(gpio15), |
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217 | + BCM6368_GROUP(gpio16), |
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218 | + BCM6368_GROUP(gpio17), |
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219 | + BCM6368_GROUP(gpio18), |
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220 | + BCM6368_GROUP(gpio19), |
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221 | + BCM6368_GROUP(gpio20), |
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222 | + BCM6368_GROUP(gpio21), |
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223 | + BCM6368_GROUP(gpio22), |
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224 | + BCM6368_GROUP(gpio23), |
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225 | + BCM6368_GROUP(gpio24), |
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226 | + BCM6368_GROUP(gpio25), |
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227 | + BCM6368_GROUP(gpio26), |
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228 | + BCM6368_GROUP(gpio27), |
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229 | + BCM6368_GROUP(gpio28), |
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230 | + BCM6368_GROUP(gpio29), |
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231 | + BCM6368_GROUP(gpio30), |
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232 | + BCM6368_GROUP(gpio31), |
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233 | + BCM6368_GROUP(uart1_grp), |
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234 | +}; |
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235 | + |
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236 | +static const char * const analog_afe_0_groups[] = { |
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237 | + "gpio0", |
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238 | +}; |
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239 | + |
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240 | +static const char * const analog_afe_1_groups[] = { |
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241 | + "gpio1", |
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242 | +}; |
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243 | + |
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244 | +static const char * const sys_irq_groups[] = { |
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245 | + "gpio2", |
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246 | +}; |
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247 | + |
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248 | +static const char * const serial_led_data_groups[] = { |
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249 | + "gpio3", |
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250 | +}; |
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251 | + |
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252 | +static const char * const serial_led_clk_groups[] = { |
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253 | + "gpio4", |
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254 | +}; |
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255 | + |
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256 | +static const char * const inet_led_groups[] = { |
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257 | + "gpio5", |
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258 | +}; |
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259 | + |
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260 | +static const char * const ephy0_led_groups[] = { |
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261 | + "gpio6", |
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262 | +}; |
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263 | + |
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264 | +static const char * const ephy1_led_groups[] = { |
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265 | + "gpio7", |
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266 | +}; |
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267 | + |
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268 | +static const char * const ephy2_led_groups[] = { |
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269 | + "gpio8", |
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270 | +}; |
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271 | + |
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272 | +static const char * const ephy3_led_groups[] = { |
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273 | + "gpio9", |
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274 | +}; |
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275 | + |
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276 | +static const char * const robosw_led_data_groups[] = { |
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277 | + "gpio10", |
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278 | +}; |
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279 | + |
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280 | +static const char * const robosw_led_clk_groups[] = { |
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281 | + "gpio11", |
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282 | +}; |
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283 | + |
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284 | +static const char * const robosw_led0_groups[] = { |
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285 | + "gpio12", |
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286 | +}; |
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287 | + |
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288 | +static const char * const robosw_led1_groups[] = { |
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289 | + "gpio13", |
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290 | +}; |
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291 | + |
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292 | +static const char * const usb_device_led_groups[] = { |
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293 | + "gpio14", |
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294 | +}; |
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295 | + |
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296 | +static const char * const pci_req1_groups[] = { |
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297 | + "gpio16", |
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298 | +}; |
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299 | + |
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300 | +static const char * const pci_gnt1_groups[] = { |
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301 | + "gpio17", |
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302 | +}; |
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303 | + |
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304 | +static const char * const pci_intb_groups[] = { |
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305 | + "gpio18", |
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306 | +}; |
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307 | + |
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308 | +static const char * const pci_req0_groups[] = { |
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309 | + "gpio19", |
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310 | +}; |
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311 | + |
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312 | +static const char * const pci_gnt0_groups[] = { |
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313 | + "gpio20", |
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314 | +}; |
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315 | + |
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316 | +static const char * const pcmcia_cd1_groups[] = { |
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317 | + "gpio22", |
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318 | +}; |
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319 | + |
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320 | +static const char * const pcmcia_cd2_groups[] = { |
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321 | + "gpio23", |
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322 | +}; |
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323 | + |
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324 | +static const char * const pcmcia_vs1_groups[] = { |
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325 | + "gpio24", |
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326 | +}; |
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327 | + |
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328 | +static const char * const pcmcia_vs2_groups[] = { |
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329 | + "gpio25", |
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330 | +}; |
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331 | + |
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332 | +static const char * const ebi_cs2_groups[] = { |
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333 | + "gpio26", |
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334 | +}; |
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335 | + |
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336 | +static const char * const ebi_cs3_groups[] = { |
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337 | + "gpio27", |
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338 | +}; |
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339 | + |
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340 | +static const char * const spi_cs2_groups[] = { |
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341 | + "gpio28", |
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342 | +}; |
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343 | + |
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344 | +static const char * const spi_cs3_groups[] = { |
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345 | + "gpio29", |
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346 | +}; |
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347 | + |
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348 | +static const char * const spi_cs4_groups[] = { |
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349 | + "gpio30", |
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350 | +}; |
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351 | + |
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352 | +static const char * const spi_cs5_groups[] = { |
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353 | + "gpio31", |
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354 | +}; |
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355 | + |
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356 | +static const char * const uart1_groups[] = { |
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357 | + "uart1_grp", |
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358 | +}; |
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359 | + |
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360 | +#define BCM6368_FUN(n, out) \ |
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361 | + { \ |
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362 | + .name = #n, \ |
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363 | + .groups = n##_groups, \ |
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364 | + .num_groups = ARRAY_SIZE(n##_groups), \ |
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365 | + .dir_out = out, \ |
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366 | + } |
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367 | + |
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368 | +#define BCM6368_BASEMODE_FUN(n, val, out) \ |
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369 | + { \ |
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370 | + .name = #n, \ |
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371 | + .groups = n##_groups, \ |
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372 | + .num_groups = ARRAY_SIZE(n##_groups), \ |
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373 | + .basemode = BCM6368_BASEMODE_##val, \ |
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374 | + .dir_out = out, \ |
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375 | + } |
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376 | + |
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377 | +static const struct bcm6368_function bcm6368_funcs[] = { |
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378 | + BCM6368_FUN(analog_afe_0, 1), |
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379 | + BCM6368_FUN(analog_afe_1, 1), |
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380 | + BCM6368_FUN(sys_irq, 1), |
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381 | + BCM6368_FUN(serial_led_data, 1), |
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382 | + BCM6368_FUN(serial_led_clk, 1), |
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383 | + BCM6368_FUN(inet_led, 1), |
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384 | + BCM6368_FUN(ephy0_led, 1), |
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385 | + BCM6368_FUN(ephy1_led, 1), |
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386 | + BCM6368_FUN(ephy2_led, 1), |
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387 | + BCM6368_FUN(ephy3_led, 1), |
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388 | + BCM6368_FUN(robosw_led_data, 1), |
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389 | + BCM6368_FUN(robosw_led_clk, 1), |
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390 | + BCM6368_FUN(robosw_led0, 1), |
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391 | + BCM6368_FUN(robosw_led1, 1), |
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392 | + BCM6368_FUN(usb_device_led, 1), |
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393 | + BCM6368_FUN(pci_req1, 0), |
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394 | + BCM6368_FUN(pci_gnt1, 0), |
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395 | + BCM6368_FUN(pci_intb, 0), |
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396 | + BCM6368_FUN(pci_req0, 0), |
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397 | + BCM6368_FUN(pci_gnt0, 0), |
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398 | + BCM6368_FUN(pcmcia_cd1, 0), |
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399 | + BCM6368_FUN(pcmcia_cd2, 0), |
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400 | + BCM6368_FUN(pcmcia_vs1, 0), |
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401 | + BCM6368_FUN(pcmcia_vs2, 0), |
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402 | + BCM6368_FUN(ebi_cs2, 1), |
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403 | + BCM6368_FUN(ebi_cs3, 1), |
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404 | + BCM6368_FUN(spi_cs2, 1), |
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405 | + BCM6368_FUN(spi_cs3, 1), |
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406 | + BCM6368_FUN(spi_cs4, 1), |
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407 | + BCM6368_FUN(spi_cs5, 1), |
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408 | + BCM6368_BASEMODE_FUN(uart1, UART1, 0x6), |
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409 | +}; |
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410 | + |
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411 | +static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev) |
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412 | +{ |
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413 | + return ARRAY_SIZE(bcm6368_groups); |
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414 | +} |
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415 | + |
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416 | +static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev, |
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417 | + unsigned group) |
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418 | +{ |
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419 | + return bcm6368_groups[group].name; |
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420 | +} |
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421 | + |
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422 | +static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, |
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423 | + unsigned group, const unsigned **pins, |
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424 | + unsigned *num_pins) |
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425 | +{ |
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426 | + *pins = bcm6368_groups[group].pins; |
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427 | + *num_pins = bcm6368_groups[group].num_pins; |
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428 | + |
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429 | + return 0; |
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430 | +} |
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431 | + |
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432 | +static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev) |
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433 | +{ |
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434 | + return ARRAY_SIZE(bcm6368_funcs); |
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435 | +} |
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436 | + |
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437 | +static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev, |
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438 | + unsigned selector) |
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439 | +{ |
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440 | + return bcm6368_funcs[selector].name; |
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441 | +} |
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442 | + |
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443 | +static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev, |
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444 | + unsigned selector, |
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445 | + const char * const **groups, |
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446 | + unsigned * const num_groups) |
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447 | +{ |
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448 | + *groups = bcm6368_funcs[selector].groups; |
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449 | + *num_groups = bcm6368_funcs[selector].num_groups; |
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450 | + |
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451 | + return 0; |
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452 | +} |
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453 | + |
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454 | +static void bcm6368_rmw_mux(struct bcm6368_pinctrl *pctl, void __iomem *reg, |
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455 | + u32 mask, u32 val) |
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456 | +{ |
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457 | + u32 tmp; |
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458 | + |
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459 | + tmp = __raw_readl(reg); |
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460 | + tmp &= ~mask; |
||
461 | + tmp |= (val & mask); |
||
462 | + __raw_writel(tmp, reg); |
||
463 | +} |
||
464 | + |
||
465 | +static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev, |
||
466 | + unsigned selector, unsigned group) |
||
467 | +{ |
||
468 | + struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
||
469 | + const struct bcm6368_pingroup *grp = &bcm6368_groups[group]; |
||
470 | + const struct bcm6368_function *fun = &bcm6368_funcs[selector]; |
||
471 | + unsigned long flags; |
||
472 | + int i, pin; |
||
473 | + |
||
474 | + spin_lock_irqsave(&pctl->lock, flags); |
||
475 | + if (fun->basemode) { |
||
476 | + u32 mask = 0; |
||
477 | + |
||
478 | + for (i = 0; i < grp->num_pins; i++) { |
||
479 | + pin = grp->pins[i]; |
||
480 | + if (pin < 32) |
||
481 | + mask |= BIT(pin); |
||
482 | + } |
||
483 | + |
||
484 | + bcm6368_rmw_mux(pctl, pctl->mode, mask, 0); |
||
485 | + regmap_field_write(pctl->overlay, fun->basemode); |
||
486 | + } else { |
||
487 | + pin = grp->pins[0]; |
||
488 | + |
||
489 | + if (bcm6368_pins[pin].drv_data) |
||
490 | + regmap_field_write(pctl->overlay, |
||
491 | + BCM6368_BASEMODE_GPIO); |
||
492 | + |
||
493 | + bcm6368_rmw_mux(pctl, pctl->mode, BIT(pin), BIT(pin)); |
||
494 | + } |
||
495 | + spin_unlock_irqrestore(&pctl->lock, flags); |
||
496 | + |
||
497 | + for (pin = 0; pin < grp->num_pins; pin++) { |
||
498 | + int hw_gpio = bcm6368_pins[pin].number; |
||
499 | + struct gpio_chip *gc = &pctl->gpio[hw_gpio / 32]; |
||
500 | + |
||
501 | + if (fun->dir_out & BIT(pin)) |
||
502 | + gc->direction_output(gc, hw_gpio % 32, 0); |
||
503 | + else |
||
504 | + gc->direction_input(gc, hw_gpio % 32); |
||
505 | + } |
||
506 | + |
||
507 | + return 0; |
||
508 | +} |
||
509 | + |
||
510 | +static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev, |
||
511 | + struct pinctrl_gpio_range *range, |
||
512 | + unsigned offset) |
||
513 | +{ |
||
514 | + struct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); |
||
515 | + unsigned long flags; |
||
516 | + |
||
517 | + if (offset >= 32 && !bcm6368_pins[offset].drv_data) |
||
518 | + return 0; |
||
519 | + |
||
520 | + spin_lock_irqsave(&pctl->lock, flags); |
||
521 | + /* disable all functions using this pin */ |
||
522 | + if (offset < 32) |
||
523 | + bcm6368_rmw_mux(pctl, pctl->mode, BIT(offset), 0); |
||
524 | + |
||
525 | + if (bcm6368_pins[offset].drv_data) |
||
526 | + regmap_field_write(pctl->overlay, BCM6368_BASEMODE_GPIO); |
||
527 | + |
||
528 | + spin_unlock_irqrestore(&pctl->lock, flags); |
||
529 | + |
||
530 | + return 0; |
||
531 | +} |
||
532 | + |
||
533 | +static struct pinctrl_ops bcm6368_pctl_ops = { |
||
534 | + .get_groups_count = bcm6368_pinctrl_get_group_count, |
||
535 | + .get_group_name = bcm6368_pinctrl_get_group_name, |
||
536 | + .get_group_pins = bcm6368_pinctrl_get_group_pins, |
||
537 | +#ifdef CONFIG_OF |
||
538 | + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, |
||
539 | + .dt_free_map = pinctrl_utils_free_map, |
||
540 | +#endif |
||
541 | +}; |
||
542 | + |
||
543 | +static struct pinmux_ops bcm6368_pmx_ops = { |
||
544 | + .get_functions_count = bcm6368_pinctrl_get_func_count, |
||
545 | + .get_function_name = bcm6368_pinctrl_get_func_name, |
||
546 | + .get_function_groups = bcm6368_pinctrl_get_groups, |
||
547 | + .set_mux = bcm6368_pinctrl_set_mux, |
||
548 | + .gpio_request_enable = bcm6368_gpio_request_enable, |
||
549 | + .strict = true, |
||
550 | +}; |
||
551 | + |
||
552 | +static int bcm6368_pinctrl_probe(struct platform_device *pdev) |
||
553 | +{ |
||
554 | + struct bcm6368_pinctrl *pctl; |
||
555 | + struct resource *res; |
||
556 | + void __iomem *mode; |
||
557 | + struct regmap *basemode; |
||
558 | + struct reg_field overlay = REG_FIELD(0, 0, 3); |
||
559 | + |
||
560 | + if (pdev->dev.of_node) |
||
561 | + basemode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
||
562 | + "brcm,gpiobasemode"); |
||
563 | + else |
||
564 | + basemode = syscon_regmap_lookup_by_pdevname("syscon.b00000b8"); |
||
565 | + |
||
566 | + if (IS_ERR(basemode)) |
||
567 | + return PTR_ERR(basemode); |
||
568 | + |
||
569 | + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode"); |
||
570 | + mode = devm_ioremap_resource(&pdev->dev, res); |
||
571 | + if (IS_ERR(mode)) |
||
572 | + return PTR_ERR(mode); |
||
573 | + |
||
574 | + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); |
||
575 | + if (!pctl) |
||
576 | + return -ENOMEM; |
||
577 | + |
||
578 | + pctl->overlay = devm_regmap_field_alloc(&pdev->dev, basemode, overlay); |
||
579 | + if (IS_ERR(pctl->overlay)) |
||
580 | + return PTR_ERR(pctl->overlay); |
||
581 | + |
||
582 | + spin_lock_init(&pctl->lock); |
||
583 | + |
||
584 | + pctl->mode = mode; |
||
585 | + |
||
586 | + /* disable all muxes by default */ |
||
587 | + __raw_writel(0, pctl->mode); |
||
588 | + |
||
589 | + pctl->desc.name = dev_name(&pdev->dev); |
||
590 | + pctl->desc.owner = THIS_MODULE; |
||
591 | + pctl->desc.pctlops = &bcm6368_pctl_ops; |
||
592 | + pctl->desc.pmxops = &bcm6368_pmx_ops; |
||
593 | + |
||
594 | + pctl->desc.npins = ARRAY_SIZE(bcm6368_pins); |
||
595 | + pctl->desc.pins = bcm6368_pins; |
||
596 | + |
||
597 | + platform_set_drvdata(pdev, pctl); |
||
598 | + |
||
599 | + pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl, |
||
600 | + pctl->gpio, BCM6368_NGPIO); |
||
601 | + if (IS_ERR(pctl->pctldev)) |
||
602 | + return PTR_ERR(pctl->pctldev); |
||
603 | + |
||
604 | + return 0; |
||
605 | +} |
||
606 | + |
||
607 | +static const struct of_device_id bcm6368_pinctrl_match[] = { |
||
608 | + { .compatible = "brcm,bcm6368-pinctrl", }, |
||
609 | + { }, |
||
610 | +}; |
||
611 | + |
||
612 | +static struct platform_driver bcm6368_pinctrl_driver = { |
||
613 | + .probe = bcm6368_pinctrl_probe, |
||
614 | + .driver = { |
||
615 | + .name = "bcm6368-pinctrl", |
||
616 | + .of_match_table = bcm6368_pinctrl_match, |
||
617 | + }, |
||
618 | +}; |
||
619 | + |
||
620 | +builtin_platform_driver(bcm6368_pinctrl_driver); |