OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | From cb86630379c8f3432c916d62045b5176f17f4123 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Sun, 16 Jul 2017 12:57:21 +0200 |
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4 | Subject: [PATCH V2 6/8] MIPS: BCM63XX: move the HSSPI PLL HZ into its own |
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5 | clock |
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6 | |||
7 | Split up the HSSPL clock into rate and a gate clock, to more closely |
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8 | match the actual hardware. |
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9 | |||
10 | Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
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11 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
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12 | --- |
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13 | arch/mips/bcm63xx/clk.c | 10 ++++++++-- |
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14 | 1 file changed, 8 insertions(+), 2 deletions(-) |
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15 | |||
16 | --- a/arch/mips/bcm63xx/clk.c |
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17 | +++ b/arch/mips/bcm63xx/clk.c |
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18 | @@ -247,6 +247,10 @@ static struct clk clk_hsspi = { |
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19 | .set = hsspi_set, |
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20 | }; |
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21 | |||
22 | +/* |
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23 | + * HSSPI PLL |
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24 | + */ |
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25 | +static struct clk clk_hsspi_pll; |
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26 | |||
27 | /* |
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28 | * XTM clock |
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29 | @@ -376,6 +380,7 @@ static struct clk_lookup bcm6328_clks[] |
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30 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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31 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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32 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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33 | + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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34 | /* gated clocks */ |
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35 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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36 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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37 | @@ -443,6 +448,7 @@ static struct clk_lookup bcm6362_clks[] |
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38 | CLKDEV_INIT(NULL, "periph", &clk_periph), |
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39 | CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph), |
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40 | CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph), |
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41 | + CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll), |
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42 | /* gated clocks */ |
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43 | CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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44 | CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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45 | @@ -477,7 +483,7 @@ static int __init bcm63xx_clk_init(void) |
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46 | clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks)); |
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47 | break; |
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48 | case BCM6328_CPU_ID: |
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49 | - clk_hsspi.rate = HSSPI_PLL_HZ_6328; |
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50 | + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6328; |
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51 | clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks)); |
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52 | break; |
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53 | case BCM6338_CPU_ID: |
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54 | @@ -493,7 +499,7 @@ static int __init bcm63xx_clk_init(void) |
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55 | clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks)); |
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56 | break; |
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57 | case BCM6362_CPU_ID: |
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58 | - clk_hsspi.rate = HSSPI_PLL_HZ_6362; |
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59 | + clk_hsspi_pll.rate = HSSPI_PLL_HZ_6362; |
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60 | clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks)); |
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61 | break; |
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62 | case BCM6368_CPU_ID: |