OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Thu, 3 May 2012 14:36:11 +0200 |
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4 | Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices |
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5 | |||
6 | --- |
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7 | arch/mips/bcm63xx/Makefile | 3 +- |
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8 | arch/mips/bcm63xx/pci-ath9k-fixup.c | 190 ++++++++++++++++++++ |
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9 | .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h | 7 + |
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10 | 3 files changed, 199 insertions(+), 1 deletion(-) |
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11 | create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c |
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12 | create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h |
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13 | |||
14 | --- a/arch/mips/bcm63xx/Makefile |
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15 | +++ b/arch/mips/bcm63xx/Makefile |
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16 | @@ -3,7 +3,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o |
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17 | setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \ |
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18 | dev-rng.o dev-wdt.o \ |
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19 | dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \ |
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20 | - sprom.o |
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21 | + pci-ath9k-fixup.o sprom.o |
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22 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
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23 | |||
24 | obj-y += boards/ |
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25 | --- /dev/null |
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26 | +++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c |
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27 | @@ -0,0 +1,200 @@ |
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28 | +/* |
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29 | + * Broadcom BCM63XX Ath9k EEPROM fixup helper. |
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30 | + * |
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31 | + * Copytight (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> |
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32 | + * |
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33 | + * Based on |
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34 | + * |
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35 | + * Atheros AP94 reference board PCI initialization |
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36 | + * |
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37 | + * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> |
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38 | + * |
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39 | + * This program is free software; you can redistribute it and/or modify it |
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40 | + * under the terms of the GNU General Public License version 2 as published |
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41 | + * by the Free Software Foundation. |
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42 | + */ |
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43 | + |
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44 | +#include <linux/if_ether.h> |
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45 | +#include <linux/pci.h> |
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46 | +#include <linux/delay.h> |
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47 | +#include <linux/ath9k_platform.h> |
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48 | + |
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49 | +#include <bcm63xx_cpu.h> |
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50 | +#include <bcm63xx_regs.h> |
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51 | +#include <bcm63xx_io.h> |
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52 | +#include <bcm63xx_nvram.h> |
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53 | +#include <bcm63xx_dev_pci.h> |
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54 | +#include <bcm63xx_dev_flash.h> |
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55 | +#include <pci_ath9k_fixup.h> |
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56 | + |
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57 | +#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o)) |
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58 | + |
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59 | +struct ath9k_fixup { |
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60 | + unsigned slot; |
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61 | + u8 mac[ETH_ALEN]; |
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62 | + struct ath9k_platform_data pdata; |
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63 | +}; |
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64 | + |
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65 | +static int ath9k_num_fixups; |
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66 | +static struct ath9k_fixup ath9k_fixups[2] = { |
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67 | + { |
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68 | + .slot = 255, |
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69 | + .pdata = { |
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70 | + .led_pin = -1, |
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71 | + }, |
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72 | + }, |
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73 | + { |
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74 | + .slot = 255, |
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75 | + .pdata = { |
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76 | + .led_pin = -1, |
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77 | + }, |
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78 | + }, |
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79 | +}; |
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80 | + |
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81 | +static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset) |
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82 | +{ |
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83 | + u32 addr; |
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84 | + |
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85 | + if (BCMCPU_IS_6328()) { |
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86 | + addr = 0x18000000; |
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87 | + } else { |
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88 | + addr = bcm_mpi_readl(MPI_CSBASE_REG(0)); |
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89 | + addr &= MPI_CSBASE_BASE_MASK; |
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90 | + } |
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91 | + |
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92 | + switch (bcm63xx_flash_get_type()) { |
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93 | + case BCM63XX_FLASH_TYPE_PARALLEL: |
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94 | + memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); |
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95 | + return eeprom; |
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96 | + case BCM63XX_FLASH_TYPE_SERIAL: |
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97 | + /* the first megabyte is memory mapped */ |
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98 | + if (offset < 0x100000) { |
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99 | + memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); |
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100 | + return eeprom; |
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101 | + } |
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102 | + |
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103 | + if (BCMCPU_IS_6328()) { |
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104 | + /* we can change the memory mapped megabyte */ |
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105 | + bcm_hsspi_writel(offset & 0xf00000, 0x18); |
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106 | + memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16)); |
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107 | + bcm_hsspi_writel(0, 0x18); |
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108 | + return eeprom; |
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109 | + } |
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110 | + /* can't do anything here without talking to the SPI controller. */ |
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111 | + case BCM63XX_FLASH_TYPE_NAND: |
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112 | + default: |
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113 | + return NULL; |
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114 | + } |
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115 | +} |
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116 | + |
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117 | +static void ath9k_pci_fixup(struct pci_dev *dev) |
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118 | +{ |
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119 | + void __iomem *mem; |
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120 | + struct ath9k_platform_data *pdata = NULL; |
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121 | + struct pci_dev *bridge = pci_upstream_bridge(dev); |
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122 | + u16 *cal_data = NULL; |
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123 | + u16 cmd; |
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124 | + u32 bar0; |
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125 | + u32 val; |
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126 | + unsigned i; |
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127 | + |
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128 | + for (i = 0; i < ath9k_num_fixups; i++) { |
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129 | + if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) |
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130 | + continue; |
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131 | + |
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132 | + cal_data = ath9k_fixups[i].pdata.eeprom_data; |
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133 | + pdata = &ath9k_fixups[i].pdata; |
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134 | + break; |
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135 | + } |
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136 | + |
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137 | + if (cal_data == NULL) |
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138 | + return; |
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139 | + |
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140 | + if (*cal_data != 0xa55a) { |
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141 | + pr_err("pci %s: invalid calibration data\n", pci_name(dev)); |
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142 | + return; |
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143 | + } |
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144 | + |
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145 | + pr_info("pci %s: fixup device configuration\n", pci_name(dev)); |
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146 | + |
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147 | + switch (bcm63xx_get_cpu_id()) { |
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148 | + case BCM6328_CPU_ID: |
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149 | + val = BCM_PCIE_MEM_BASE_PA_6328; |
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150 | + break; |
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151 | + case BCM6348_CPU_ID: |
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152 | + case BCM6358_CPU_ID: |
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153 | + case BCM6368_CPU_ID: |
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154 | + val = BCM_PCI_MEM_BASE_PA; |
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155 | + break; |
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156 | + default: |
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157 | + BUG(); |
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158 | + } |
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159 | + |
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160 | + mem = ioremap(val, 0x10000); |
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161 | + if (!mem) { |
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162 | + pr_err("pci %s: ioremap error\n", pci_name(dev)); |
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163 | + return; |
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164 | + } |
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165 | + |
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166 | + if (bridge) |
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167 | + pci_enable_device(bridge); |
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168 | + |
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169 | + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); |
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170 | + pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); |
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171 | + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val); |
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172 | + |
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173 | + pci_read_config_word(dev, PCI_COMMAND, &cmd); |
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174 | + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
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175 | + pci_write_config_word(dev, PCI_COMMAND, cmd); |
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176 | + |
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177 | + /* set offset to first reg address */ |
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178 | + cal_data += 3; |
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179 | + while(*cal_data != 0xffff) { |
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180 | + u32 reg; |
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181 | + reg = *cal_data++; |
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182 | + val = *cal_data++; |
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183 | + val |= (*cal_data++) << 16; |
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184 | + |
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185 | + writel(val, mem + reg); |
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186 | + udelay(100); |
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187 | + } |
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188 | + |
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189 | + pci_read_config_dword(dev, PCI_VENDOR_ID, &val); |
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190 | + dev->vendor = val & 0xffff; |
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191 | + dev->device = (val >> 16) & 0xffff; |
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192 | + |
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193 | + pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); |
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194 | + dev->revision = val & 0xff; |
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195 | + dev->class = val >> 8; /* upper 3 bytes */ |
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196 | + |
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197 | + pci_read_config_word(dev, PCI_COMMAND, &cmd); |
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198 | + cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
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199 | + pci_write_config_word(dev, PCI_COMMAND, cmd); |
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200 | + |
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201 | + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); |
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202 | + |
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203 | + if (bridge) |
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204 | + pci_disable_device(bridge); |
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205 | + |
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206 | + iounmap(mem); |
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207 | + |
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208 | + dev->dev.platform_data = pdata; |
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209 | +} |
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210 | +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); |
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211 | + |
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212 | +void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset) |
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213 | +{ |
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214 | + if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) |
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215 | + return; |
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216 | + |
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217 | + ath9k_fixups[ath9k_num_fixups].slot = slot; |
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218 | + |
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219 | + if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset)) |
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220 | + return; |
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221 | + |
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222 | + if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac)) |
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223 | + return; |
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224 | + |
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225 | + ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac; |
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226 | + ath9k_num_fixups++; |
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227 | +} |
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228 | --- /dev/null |
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229 | +++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h |
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230 | @@ -0,0 +1,7 @@ |
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231 | +#ifndef _PCI_ATH9K_FIXUP |
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232 | +#define _PCI_ATH9K_FIXUP |
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233 | + |
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234 | + |
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235 | +void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init; |
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236 | + |
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237 | +#endif /* _PCI_ATH9K_FIXUP */ |