OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
2 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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3 | @@ -1034,11 +1034,18 @@ |
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4 | #define USBH_PRIV_SETUP_6368_REG 0x28 |
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5 | #define USBH_PRIV_SETUP_IOC_SHIFT 4 |
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6 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) |
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7 | +#define USBH_PRIV_SETUP_IPP_SHIFT 5 |
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8 | +#define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT) |
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9 | |||
10 | #define USBH_PRIV_SETUP_6318_REG 0x00 |
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11 | +#define USBH_PRIV_PLL_CTRL1_6368_REG 0x18 |
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12 | #define USBH_PRIV_PLL_CTRL1_6318_REG 0x04 |
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13 | -#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27) |
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14 | -#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31) |
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15 | + |
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16 | +#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27) |
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17 | +#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31) |
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18 | +#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9) |
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19 | +#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY (1 << 10) |
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20 | + |
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21 | #define USBH_PRIV_SIM_CTRL_6318_REG 0x20 |
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22 | #define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5) |
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23 | |||
24 | --- a/arch/mips/bcm63xx/Kconfig |
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25 | +++ b/arch/mips/bcm63xx/Kconfig |
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26 | @@ -73,6 +73,8 @@ config BCM63XX_CPU_63268 |
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27 | bool "support 63268 CPU" |
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28 | select SYS_HAS_CPU_BMIPS4350 |
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29 | select HW_HAS_PCI |
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30 | + select BCM63XX_OHCI |
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31 | + select BCM63XX_EHCI |
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32 | endmenu |
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33 | |||
34 | source "arch/mips/bcm63xx/boards/Kconfig" |
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35 | --- a/arch/mips/bcm63xx/dev-usb-ehci.c |
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36 | +++ b/arch/mips/bcm63xx/dev-usb-ehci.c |
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37 | @@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh |
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38 | int __init bcm63xx_ehci_register(void) |
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39 | { |
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40 | if (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() && |
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41 | - !BCMCPU_IS_6362() && !BCMCPU_IS_6368()) |
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42 | + !BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268()) |
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43 | return 0; |
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44 | |||
45 | ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); |
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46 | --- a/arch/mips/bcm63xx/usb-common.c |
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47 | +++ b/arch/mips/bcm63xx/usb-common.c |
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48 | @@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) |
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49 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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50 | reg |= USBH_PRIV_SETUP_IOC_MASK; |
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51 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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52 | + } else if (BCMCPU_IS_63268()) { |
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53 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); |
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54 | + reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; |
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55 | + reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; |
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56 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); |
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57 | + |
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58 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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59 | + reg |= USBH_PRIV_SETUP_IOC_MASK; |
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60 | + reg &= ~USBH_PRIV_SETUP_IPP_MASK; |
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61 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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62 | + |
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63 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); |
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64 | + reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | |
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65 | + USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); |
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66 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); |
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67 | } else if (BCMCPU_IS_6318()) { |
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68 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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69 | - reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; |
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70 | + reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; |
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71 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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72 | |||
73 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); |
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74 | @@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void) |
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75 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); |
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76 | |||
77 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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78 | - reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; |
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79 | + reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; |
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80 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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81 | |||
82 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); |
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83 | @@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) |
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84 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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85 | reg |= USBH_PRIV_SETUP_IOC_MASK; |
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86 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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87 | + } else if (BCMCPU_IS_63268()) { |
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88 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG); |
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89 | + reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK; |
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90 | + reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK; |
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91 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG); |
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92 | + |
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93 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG); |
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94 | + reg |= USBH_PRIV_SETUP_IOC_MASK; |
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95 | + reg &= ~USBH_PRIV_SETUP_IPP_MASK; |
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96 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG); |
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97 | + |
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98 | + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG); |
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99 | + reg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN | |
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100 | + USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY); |
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101 | + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG); |
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102 | } else if (BCMCPU_IS_6318()) { |
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103 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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104 | - reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN; |
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105 | + reg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN; |
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106 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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107 | |||
108 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG); |
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109 | @@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void) |
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110 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG); |
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111 | |||
112 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG); |
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113 | - reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN; |
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114 | + reg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN; |
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115 | bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG); |
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116 | |||
117 | reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG); |