OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
2 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |
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3 | @@ -587,6 +587,9 @@ |
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4 | #define TIMER_CTL_MONOTONIC_MASK (1 << 30) |
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5 | #define TIMER_CTL_ENABLE_MASK (1 << 31) |
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6 | |||
7 | +/* Clock reset control (63268 only) */ |
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8 | +#define TIMER_CLK_RST_CTL_REG 0x2c |
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9 | +#define CLK_RST_CTL_USB_REF_CLK_EN (1 << 18) |
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10 | |||
11 | /************************************************************************* |
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12 | * _REG relative to RSET_WDT |
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13 | @@ -1534,6 +1537,11 @@ |
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14 | #define STRAPBUS_63268_FCVO_SHIFT 21 |
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15 | #define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT) |
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16 | |||
17 | +#define MISC_IDDQ_CTRL_6328_REG 0x48 |
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18 | +#define MISC_IDDQ_CTRL_63268_REG 0x4c |
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19 | + |
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20 | +#define IDDQ_CTRL_63268_USBH (1 << 4) |
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21 | + |
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22 | #define MISC_STRAPBUS_6328_REG 0x240 |
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23 | #define STRAPBUS_6328_FCVO_SHIFT 7 |
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24 | #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) |
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25 | --- a/arch/mips/bcm63xx/clk.c |
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26 | +++ b/arch/mips/bcm63xx/clk.c |
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27 | @@ -64,6 +64,26 @@ static void bcm_ub_hwclock_set(u32 mask, |
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28 | bcm_perf_writel(reg, PERF_UB_CKCTL_REG); |
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29 | } |
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30 | |||
31 | +static void bcm_misc_iddq_set(u32 mask, int enable) |
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32 | +{ |
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33 | + u32 offset; |
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34 | + u32 reg; |
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35 | + |
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36 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) |
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37 | + offset = MISC_IDDQ_CTRL_6328_REG; |
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38 | + else if (BCMCPU_IS_63268()) |
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39 | + offset = MISC_IDDQ_CTRL_63268_REG; |
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40 | + else |
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41 | + return; |
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42 | + |
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43 | + reg = bcm_misc_readl(offset); |
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44 | + if (enable) |
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45 | + reg &= ~mask; |
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46 | + else |
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47 | + reg |= mask; |
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48 | + bcm_misc_writel(reg, offset); |
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49 | +} |
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50 | + |
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51 | /* |
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52 | * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 |
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53 | */ |
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54 | @@ -236,7 +256,17 @@ static void usbh_set(struct clk *clk, in |
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55 | } else if (BCMCPU_IS_6368()) { |
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56 | bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); |
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57 | } else if (BCMCPU_IS_63268()) { |
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58 | + u32 reg; |
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59 | + |
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60 | bcm_hwclock_set(CKCTL_63268_USBH_EN, enable); |
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61 | + bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable); |
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62 | + bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable); |
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63 | + reg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG); |
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64 | + if (enable) |
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65 | + reg |= CLK_RST_CTL_USB_REF_CLK_EN; |
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66 | + else |
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67 | + reg &= ~CLK_RST_CTL_USB_REF_CLK_EN; |
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68 | + bcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG); |
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69 | } else { |
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70 | return; |
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71 | } |