OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jogo@openwrt.org> |
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3 | Date: Sun, 8 Dec 2013 03:13:06 +0100 |
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4 | Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows |
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5 | |||
6 | Different SoCs use different memory windows (and sizes), so don't |
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7 | hardcode it. |
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8 | --- |
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9 | arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 8 ++++---- |
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10 | arch/mips/pci/pci-bcm63xx.c | 15 ++++++++++----- |
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11 | 2 files changed, 14 insertions(+), 9 deletions(-) |
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12 | |||
13 | --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |
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14 | +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |
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15 | @@ -41,10 +41,10 @@ |
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16 | #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ |
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17 | BCM_CB_MEM_SIZE - 1) |
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18 | |||
19 | -#define BCM_PCIE_MEM_BASE_PA 0x10f00000 |
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20 | -#define BCM_PCIE_MEM_SIZE (1 * 1024 * 1024) |
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21 | -#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ |
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22 | - BCM_PCIE_MEM_SIZE - 1) |
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23 | +#define BCM_PCIE_MEM_BASE_PA_6328 0x10f00000 |
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24 | +#define BCM_PCIE_MEM_SIZE_6328 (1 * 1024 * 1024) |
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25 | +#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \ |
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26 | + BCM_PCIE_MEM_SIZE_6328 - 1) |
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27 | |||
28 | /* |
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29 | * Internal registers are accessed through KSEG3 |
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30 | --- a/arch/mips/pci/pci-bcm63xx.c |
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31 | +++ b/arch/mips/pci/pci-bcm63xx.c |
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32 | @@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control |
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33 | |||
34 | static struct resource bcm_pcie_mem_resource = { |
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35 | .name = "bcm63xx PCIe memory space", |
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36 | - .start = BCM_PCIE_MEM_BASE_PA, |
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37 | - .end = BCM_PCIE_MEM_END_PA, |
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38 | + .start = 0, |
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39 | + .end = 0, |
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40 | .flags = IORESOURCE_MEM, |
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41 | }; |
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42 | |||
43 | @@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie( |
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44 | bcm_pcie_writel(val, PCIE_CONFIG2_REG); |
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45 | |||
46 | /* set bar0 to little endian */ |
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47 | - val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; |
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48 | - val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; |
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49 | + val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT; |
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50 | + val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT; |
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51 | val |= BASEMASK_REMAP_EN; |
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52 | bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); |
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53 | |||
54 | - val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; |
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55 | + val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT; |
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56 | bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); |
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57 | |||
58 | register_pci_controller(&bcm63xx_pcie_controller); |
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59 | @@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void) |
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60 | if (!bcm63xx_pci_enabled) |
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61 | return -ENODEV; |
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62 | |||
63 | + if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) { |
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64 | + bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328; |
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65 | + bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328; |
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66 | + } |
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67 | + |
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68 | switch (bcm63xx_get_cpu_id()) { |
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69 | case BCM6328_CPU_ID: |
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70 | case BCM6362_CPU_ID: |