OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | From e74caf41aec5338b8cbbd0a1483650848f16f532 Mon Sep 17 00:00:00 2001 |
2 | From: Jonas Gorski <jonas.gorski@gmail.com> |
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3 | Date: Sun, 16 Jul 2017 12:23:47 +0200 |
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4 | Subject: [PATCH V2 1/8] MIPS: BCM63XX: add clkdev lookup support |
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5 | |||
6 | Enable clkdev lookup support to allow us providing clocks under |
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7 | different names to devices more easily, so we don't need to care |
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8 | about clock name clashes anymore. |
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9 | |||
10 | Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> |
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11 | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> |
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12 | --- |
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13 | arch/mips/Kconfig | 1 + |
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14 | arch/mips/bcm63xx/clk.c | 150 +++++++++++++++++++++++++++++++++++++----------- |
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15 | 2 files changed, 116 insertions(+), 35 deletions(-) |
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16 | |||
17 | --- a/arch/mips/Kconfig |
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18 | +++ b/arch/mips/Kconfig |
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3 | office | 19 | @@ -278,6 +278,7 @@ config BCM63XX |
1 | office | 20 | select GPIOLIB |
21 | select HAVE_CLK |
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22 | select MIPS_L1_CACHE_SHIFT_4 |
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23 | + select CLKDEV_LOOKUP |
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24 | help |
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25 | Support for BCM63XX based boards |
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26 | |||
27 | --- a/arch/mips/bcm63xx/clk.c |
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28 | +++ b/arch/mips/bcm63xx/clk.c |
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29 | @@ -11,6 +11,7 @@ |
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30 | #include <linux/mutex.h> |
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31 | #include <linux/err.h> |
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32 | #include <linux/clk.h> |
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33 | +#include <linux/clkdev.h> |
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34 | #include <linux/delay.h> |
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35 | #include <bcm63xx_cpu.h> |
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36 | #include <bcm63xx_io.h> |
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37 | @@ -359,44 +360,103 @@ long clk_round_rate(struct clk *clk, uns |
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38 | } |
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39 | EXPORT_SYMBOL_GPL(clk_round_rate); |
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40 | |||
41 | -struct clk *clk_get(struct device *dev, const char *id) |
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42 | -{ |
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43 | - if (!strcmp(id, "enet0")) |
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44 | - return &clk_enet0; |
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45 | - if (!strcmp(id, "enet1")) |
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46 | - return &clk_enet1; |
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47 | - if (!strcmp(id, "enetsw")) |
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48 | - return &clk_enetsw; |
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49 | - if (!strcmp(id, "ephy")) |
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50 | - return &clk_ephy; |
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51 | - if (!strcmp(id, "usbh")) |
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52 | - return &clk_usbh; |
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53 | - if (!strcmp(id, "usbd")) |
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54 | - return &clk_usbd; |
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55 | - if (!strcmp(id, "spi")) |
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56 | - return &clk_spi; |
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57 | - if (!strcmp(id, "hsspi")) |
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58 | - return &clk_hsspi; |
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59 | - if (!strcmp(id, "xtm")) |
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60 | - return &clk_xtm; |
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61 | - if (!strcmp(id, "periph")) |
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62 | - return &clk_periph; |
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63 | - if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm")) |
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64 | - return &clk_pcm; |
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65 | - if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) |
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66 | - return &clk_ipsec; |
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67 | - if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie")) |
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68 | - return &clk_pcie; |
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69 | - return ERR_PTR(-ENOENT); |
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70 | -} |
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71 | - |
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72 | -EXPORT_SYMBOL(clk_get); |
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73 | - |
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74 | -void clk_put(struct clk *clk) |
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75 | -{ |
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76 | -} |
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77 | - |
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78 | -EXPORT_SYMBOL(clk_put); |
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79 | +static struct clk_lookup bcm3368_clks[] = { |
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80 | + /* fixed rate clocks */ |
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81 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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82 | + /* gated clocks */ |
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83 | + CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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84 | + CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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85 | + CLKDEV_INIT(NULL, "ephy", &clk_ephy), |
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86 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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87 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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88 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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89 | + CLKDEV_INIT(NULL, "pcm", &clk_pcm), |
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90 | +}; |
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91 | + |
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92 | +static struct clk_lookup bcm6328_clks[] = { |
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93 | + /* fixed rate clocks */ |
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94 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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95 | + /* gated clocks */ |
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96 | + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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97 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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98 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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99 | + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi), |
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100 | + CLKDEV_INIT(NULL, "pcie", &clk_pcie), |
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101 | +}; |
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102 | + |
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103 | +static struct clk_lookup bcm6338_clks[] = { |
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104 | + /* fixed rate clocks */ |
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105 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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106 | + /* gated clocks */ |
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107 | + CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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108 | + CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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109 | + CLKDEV_INIT(NULL, "ephy", &clk_ephy), |
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110 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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111 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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112 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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113 | +}; |
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114 | + |
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115 | +static struct clk_lookup bcm6345_clks[] = { |
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116 | + /* fixed rate clocks */ |
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117 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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118 | + /* gated clocks */ |
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119 | + CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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120 | + CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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121 | + CLKDEV_INIT(NULL, "ephy", &clk_ephy), |
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122 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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123 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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124 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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125 | +}; |
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126 | + |
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127 | +static struct clk_lookup bcm6348_clks[] = { |
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128 | + /* fixed rate clocks */ |
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129 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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130 | + /* gated clocks */ |
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131 | + CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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132 | + CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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133 | + CLKDEV_INIT(NULL, "ephy", &clk_ephy), |
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134 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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135 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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136 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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137 | +}; |
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138 | + |
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139 | +static struct clk_lookup bcm6358_clks[] = { |
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140 | + /* fixed rate clocks */ |
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141 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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142 | + /* gated clocks */ |
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143 | + CLKDEV_INIT(NULL, "enet0", &clk_enet0), |
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144 | + CLKDEV_INIT(NULL, "enet1", &clk_enet1), |
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145 | + CLKDEV_INIT(NULL, "ephy", &clk_ephy), |
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146 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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147 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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148 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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149 | + CLKDEV_INIT(NULL, "pcm", &clk_pcm), |
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150 | +}; |
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151 | + |
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152 | +static struct clk_lookup bcm6362_clks[] = { |
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153 | + /* fixed rate clocks */ |
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154 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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155 | + /* gated clocks */ |
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156 | + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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157 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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158 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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159 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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160 | + CLKDEV_INIT(NULL, "hsspi", &clk_hsspi), |
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161 | + CLKDEV_INIT(NULL, "pcie", &clk_pcie), |
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162 | + CLKDEV_INIT(NULL, "ipsec", &clk_ipsec), |
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163 | +}; |
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164 | + |
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165 | +static struct clk_lookup bcm6368_clks[] = { |
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166 | + /* fixed rate clocks */ |
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167 | + CLKDEV_INIT(NULL, "periph", &clk_periph), |
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168 | + /* gated clocks */ |
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169 | + CLKDEV_INIT(NULL, "enetsw", &clk_enetsw), |
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170 | + CLKDEV_INIT(NULL, "usbh", &clk_usbh), |
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171 | + CLKDEV_INIT(NULL, "usbd", &clk_usbd), |
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172 | + CLKDEV_INIT(NULL, "spi", &clk_spi), |
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173 | + CLKDEV_INIT(NULL, "xtm", &clk_xtm), |
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174 | + CLKDEV_INIT(NULL, "ipsec", &clk_ipsec), |
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175 | +}; |
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176 | |||
177 | #define HSSPI_PLL_HZ_6328 133333333 |
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178 | #define HSSPI_PLL_HZ_6362 400000000 |
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179 | @@ -404,11 +464,31 @@ EXPORT_SYMBOL(clk_put); |
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180 | static int __init bcm63xx_clk_init(void) |
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181 | { |
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182 | switch (bcm63xx_get_cpu_id()) { |
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183 | + case BCM3368_CPU_ID: |
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184 | + clkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks)); |
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185 | + break; |
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186 | case BCM6328_CPU_ID: |
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187 | clk_hsspi.rate = HSSPI_PLL_HZ_6328; |
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188 | + clkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks)); |
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189 | + break; |
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190 | + case BCM6338_CPU_ID: |
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191 | + clkdev_add_table(bcm6338_clks, ARRAY_SIZE(bcm6338_clks)); |
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192 | + break; |
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193 | + case BCM6345_CPU_ID: |
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194 | + clkdev_add_table(bcm6345_clks, ARRAY_SIZE(bcm6345_clks)); |
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195 | + break; |
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196 | + case BCM6348_CPU_ID: |
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197 | + clkdev_add_table(bcm6348_clks, ARRAY_SIZE(bcm6348_clks)); |
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198 | + break; |
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199 | + case BCM6358_CPU_ID: |
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200 | + clkdev_add_table(bcm6358_clks, ARRAY_SIZE(bcm6358_clks)); |
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201 | break; |
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202 | case BCM6362_CPU_ID: |
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203 | clk_hsspi.rate = HSSPI_PLL_HZ_6362; |
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204 | + clkdev_add_table(bcm6362_clks, ARRAY_SIZE(bcm6362_clks)); |
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205 | + break; |
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206 | + case BCM6368_CPU_ID: |
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207 | + clkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks)); |
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208 | break; |
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209 | } |
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210 |