OpenWrt – Blame information for rev 2

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1 office 1 From 3765b1f79593a0a9098ed15e48074c95403a53ee Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Sat, 23 Jun 2018 15:05:08 +0200
4 Subject: [PATCH 27/33] MIPS: ath79: drop legacy IRQ code
5  
6 With the target now being fully OF based, we can drop the legacy IRQ code.
7 All IRQs are now handled via the new irqchip drivers.
8  
9 Signed-off-by: John Crispin <john@phrozen.org>
10 ---
11 arch/mips/ath79/Makefile | 2 +-
12 arch/mips/ath79/irq.c | 169 -------------------------------
13 arch/mips/ath79/setup.c | 6 ++
14 arch/mips/include/asm/mach-ath79/ath79.h | 4 -
15 4 files changed, 7 insertions(+), 174 deletions(-)
16 delete mode 100644 arch/mips/ath79/irq.c
17  
18 --- a/arch/mips/ath79/Makefile
19 +++ b/arch/mips/ath79/Makefile
20 @@ -8,7 +8,7 @@
21 # under the terms of the GNU General Public License version 2 as published
22 # by the Free Software Foundation.
23  
24 -obj-y := prom.o setup.o irq.o common.o clock.o
25 +obj-y := prom.o setup.o common.o clock.o
26  
27 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
28 obj-$(CONFIG_PCI) += pci.o
29 --- a/arch/mips/ath79/irq.c
30 +++ /dev/null
31 @@ -1,169 +0,0 @@
32 -/*
33 - * Atheros AR71xx/AR724x/AR913x specific interrupt handling
34 - *
35 - * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
36 - * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
37 - * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
38 - *
39 - * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
40 - *
41 - * This program is free software; you can redistribute it and/or modify it
42 - * under the terms of the GNU General Public License version 2 as published
43 - * by the Free Software Foundation.
44 - */
45 -
46 -#include <linux/kernel.h>
47 -#include <linux/init.h>
48 -#include <linux/interrupt.h>
49 -#include <linux/irqchip.h>
50 -#include <linux/of_irq.h>
51 -
52 -#include <asm/irq_cpu.h>
53 -#include <asm/mipsregs.h>
54 -
55 -#include <asm/mach-ath79/ath79.h>
56 -#include <asm/mach-ath79/ar71xx_regs.h>
57 -#include "common.h"
58 -#include "machtypes.h"
59 -
60 -
61 -static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
62 -{
63 - u32 status;
64 -
65 - status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
66 -
67 - if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
68 - ath79_ddr_wb_flush(3);
69 - generic_handle_irq(ATH79_IP2_IRQ(0));
70 - } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
71 - ath79_ddr_wb_flush(4);
72 - generic_handle_irq(ATH79_IP2_IRQ(1));
73 - } else {
74 - spurious_interrupt();
75 - }
76 -}
77 -
78 -static void ar934x_ip2_irq_init(void)
79 -{
80 - int i;
81 -
82 - for (i = ATH79_IP2_IRQ_BASE;
83 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
84 - irq_set_chip_and_handler(i, &dummy_irq_chip,
85 - handle_level_irq);
86 -
87 - irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
88 -}
89 -
90 -static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
91 -{
92 - u32 status;
93 -
94 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
95 - status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
96 -
97 - if (status == 0) {
98 - spurious_interrupt();
99 - return;
100 - }
101 -
102 - if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
103 - /* TODO: flush DDR? */
104 - generic_handle_irq(ATH79_IP2_IRQ(0));
105 - }
106 -
107 - if (status & QCA955X_EXT_INT_WMAC_ALL) {
108 - /* TODO: flush DDR? */
109 - generic_handle_irq(ATH79_IP2_IRQ(1));
110 - }
111 -}
112 -
113 -static void qca955x_ip3_irq_dispatch(struct irq_desc *desc)
114 -{
115 - u32 status;
116 -
117 - status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
118 - status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
119 - QCA955X_EXT_INT_USB1 |
120 - QCA955X_EXT_INT_USB2;
121 -
122 - if (status == 0) {
123 - spurious_interrupt();
124 - return;
125 - }
126 -
127 - if (status & QCA955X_EXT_INT_USB1) {
128 - /* TODO: flush DDR? */
129 - generic_handle_irq(ATH79_IP3_IRQ(0));
130 - }
131 -
132 - if (status & QCA955X_EXT_INT_USB2) {
133 - /* TODO: flush DDR? */
134 - generic_handle_irq(ATH79_IP3_IRQ(1));
135 - }
136 -
137 - if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
138 - /* TODO: flush DDR? */
139 - generic_handle_irq(ATH79_IP3_IRQ(2));
140 - }
141 -}
142 -
143 -static void qca955x_irq_init(void)
144 -{
145 - int i;
146 -
147 - for (i = ATH79_IP2_IRQ_BASE;
148 - i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
149 - irq_set_chip_and_handler(i, &dummy_irq_chip,
150 - handle_level_irq);
151 -
152 - irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
153 -
154 - for (i = ATH79_IP3_IRQ_BASE;
155 - i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
156 - irq_set_chip_and_handler(i, &dummy_irq_chip,
157 - handle_level_irq);
158 -
159 - irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
160 -}
161 -
162 -void __init arch_init_irq(void)
163 -{
164 - unsigned irq_wb_chan2 = -1;
165 - unsigned irq_wb_chan3 = -1;
166 - bool misc_is_ar71xx;
167 -
168 - if (mips_machtype == ATH79_MACH_GENERIC_OF) {
169 - irqchip_init();
170 - return;
171 - }
172 -
173 - if (soc_is_ar71xx() || soc_is_ar724x() ||
174 - soc_is_ar913x() || soc_is_ar933x()) {
175 - irq_wb_chan2 = 3;
176 - irq_wb_chan3 = 2;
177 - } else if (soc_is_ar934x()) {
178 - irq_wb_chan3 = 2;
179 - }
180 -
181 - ath79_cpu_irq_init(irq_wb_chan2, irq_wb_chan3);
182 -
183 - if (soc_is_ar71xx() || soc_is_ar913x())
184 - misc_is_ar71xx = true;
185 - else if (soc_is_ar724x() ||
186 - soc_is_ar933x() ||
187 - soc_is_ar934x() ||
188 - soc_is_qca955x())
189 - misc_is_ar71xx = false;
190 - else
191 - BUG();
192 - ath79_misc_irq_init(
193 - ath79_reset_base + AR71XX_RESET_REG_MISC_INT_STATUS,
194 - ATH79_CPU_IRQ(6), ATH79_MISC_IRQ_BASE, misc_is_ar71xx);
195 -
196 - if (soc_is_ar934x())
197 - ar934x_ip2_irq_init();
198 - else if (soc_is_qca955x())
199 - qca955x_irq_init();
200 -}
201 --- a/arch/mips/ath79/setup.c
202 +++ b/arch/mips/ath79/setup.c
203 @@ -19,6 +19,7 @@
204 #include <linux/clk.h>
205 #include <linux/clk-provider.h>
206 #include <linux/of_fdt.h>
207 +#include <linux/irqchip.h>
208  
209 #include <asm/bootinfo.h>
210 #include <asm/idle.h>
211 @@ -311,6 +312,11 @@ void __init plat_time_init(void)
212 mips_hpt_frequency = cpu_clk_rate / 2;
213 }
214  
215 +void __init arch_init_irq(void)
216 +{
217 + irqchip_init();
218 +}
219 +
220 static int __init ath79_setup(void)
221 {
222 if (mips_machtype == ATH79_MACH_GENERIC_OF)
223 --- a/arch/mips/include/asm/mach-ath79/ath79.h
224 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
225 @@ -178,8 +178,4 @@ static inline u32 ath79_reset_rr(unsigne
226 void ath79_device_reset_set(u32 mask);
227 void ath79_device_reset_clear(u32 mask);
228  
229 -void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
230 -void ath79_misc_irq_init(void __iomem *regs, int irq,
231 - int irq_base, bool is_ar71xx);
232 -
233 #endif /* __ASM_MACH_ATH79_H */