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1 office 1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11  
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/of_mdio.h>
16 #include <linux/of_net.h>
17 #include <linux/phy.h>
18 #include <linux/mii.h>
19 #include <linux/bitops.h>
20 #include <linux/switch.h>
21 #include "ag71xx.h"
22  
23 #define BITM(_count) (BIT(_count) - 1)
24 #define BITS(_shift, _count) (BITM(_count) << _shift)
25  
26 #define AR7240_REG_MASK_CTRL 0x00
27 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
28 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
29 #define AR7240_MASK_CTRL_VERSION_S 8
30 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
31 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
32 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
33  
34 #define AR7240_REG_MAC_ADDR0 0x20
35 #define AR7240_REG_MAC_ADDR1 0x24
36  
37 #define AR7240_REG_FLOOD_MASK 0x2c
38 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
39  
40 #define AR7240_REG_GLOBAL_CTRL 0x30
41 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
42 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
43  
44 #define AR7240_REG_VTU 0x0040
45 #define AR7240_VTU_OP BITM(3)
46 #define AR7240_VTU_OP_NOOP 0x0
47 #define AR7240_VTU_OP_FLUSH 0x1
48 #define AR7240_VTU_OP_LOAD 0x2
49 #define AR7240_VTU_OP_PURGE 0x3
50 #define AR7240_VTU_OP_REMOVE_PORT 0x4
51 #define AR7240_VTU_ACTIVE BIT(3)
52 #define AR7240_VTU_FULL BIT(4)
53 #define AR7240_VTU_PORT BITS(8, 4)
54 #define AR7240_VTU_PORT_S 8
55 #define AR7240_VTU_VID BITS(16, 12)
56 #define AR7240_VTU_VID_S 16
57 #define AR7240_VTU_PRIO BITS(28, 3)
58 #define AR7240_VTU_PRIO_S 28
59 #define AR7240_VTU_PRIO_EN BIT(31)
60  
61 #define AR7240_REG_VTU_DATA 0x0044
62 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
63 #define AR7240_VTUDATA_VALID BIT(11)
64  
65 #define AR7240_REG_ATU 0x50
66 #define AR7240_ATU_FLUSH_ALL 0x1
67  
68 #define AR7240_REG_AT_CTRL 0x5c
69 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
70 #define AR7240_AT_CTRL_AGE_EN BIT(17)
71 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
72 #define AR7240_AT_CTRL_RESERVED BIT(19)
73 #define AR7240_AT_CTRL_ARP_EN BIT(20)
74  
75 #define AR7240_REG_TAG_PRIORITY 0x70
76  
77 #define AR7240_REG_SERVICE_TAG 0x74
78 #define AR7240_SERVICE_TAG_M BITM(16)
79  
80 #define AR7240_REG_CPU_PORT 0x78
81 #define AR7240_MIRROR_PORT_S 4
82 #define AR7240_MIRROR_PORT_M BITM(4)
83 #define AR7240_CPU_PORT_EN BIT(8)
84  
85 #define AR7240_REG_MIB_FUNCTION0 0x80
86 #define AR7240_MIB_TIMER_M BITM(16)
87 #define AR7240_MIB_AT_HALF_EN BIT(16)
88 #define AR7240_MIB_BUSY BIT(17)
89 #define AR7240_MIB_FUNC_S 24
90 #define AR7240_MIB_FUNC_M BITM(3)
91 #define AR7240_MIB_FUNC_NO_OP 0x0
92 #define AR7240_MIB_FUNC_FLUSH 0x1
93 #define AR7240_MIB_FUNC_CAPTURE 0x3
94  
95 #define AR7240_REG_MDIO_CTRL 0x98
96 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
97 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
98 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
99 #define AR7240_MDIO_CTRL_CMD_WRITE 0
100 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
101 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
102 #define AR7240_MDIO_CTRL_BUSY BIT(31)
103  
104 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
105  
106 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
107 #define AR7240_PORT_STATUS_SPEED_S 0
108 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
109 #define AR7240_PORT_STATUS_SPEED_10 0
110 #define AR7240_PORT_STATUS_SPEED_100 1
111 #define AR7240_PORT_STATUS_SPEED_1000 2
112 #define AR7240_PORT_STATUS_TXMAC BIT(2)
113 #define AR7240_PORT_STATUS_RXMAC BIT(3)
114 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
115 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
116 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
117 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
118 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
119 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
120  
121 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
122 #define AR7240_PORT_CTRL_STATE_M BITM(3)
123 #define AR7240_PORT_CTRL_STATE_DISABLED 0
124 #define AR7240_PORT_CTRL_STATE_BLOCK 1
125 #define AR7240_PORT_CTRL_STATE_LISTEN 2
126 #define AR7240_PORT_CTRL_STATE_LEARN 3
127 #define AR7240_PORT_CTRL_STATE_FORWARD 4
128 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
129 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
130 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
131 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
132 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
133 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
134 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
135 #define AR7240_PORT_CTRL_HEADER BIT(11)
136 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
137 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
138 #define AR7240_PORT_CTRL_LEARN BIT(14)
139 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
140 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
141 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
142  
143 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
144  
145 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
146 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
147 #define AR7240_PORT_VLAN_MODE_S 30
148 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
149 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
150 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
151 #define AR7240_PORT_VLAN_MODE_SECURE 3
152  
153  
154 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
155  
156 #define AR7240_STATS_RXBROAD 0x00
157 #define AR7240_STATS_RXPAUSE 0x04
158 #define AR7240_STATS_RXMULTI 0x08
159 #define AR7240_STATS_RXFCSERR 0x0c
160 #define AR7240_STATS_RXALIGNERR 0x10
161 #define AR7240_STATS_RXRUNT 0x14
162 #define AR7240_STATS_RXFRAGMENT 0x18
163 #define AR7240_STATS_RX64BYTE 0x1c
164 #define AR7240_STATS_RX128BYTE 0x20
165 #define AR7240_STATS_RX256BYTE 0x24
166 #define AR7240_STATS_RX512BYTE 0x28
167 #define AR7240_STATS_RX1024BYTE 0x2c
168 #define AR7240_STATS_RX1518BYTE 0x30
169 #define AR7240_STATS_RXMAXBYTE 0x34
170 #define AR7240_STATS_RXTOOLONG 0x38
171 #define AR7240_STATS_RXGOODBYTE 0x3c
172 #define AR7240_STATS_RXBADBYTE 0x44
173 #define AR7240_STATS_RXOVERFLOW 0x4c
174 #define AR7240_STATS_FILTERED 0x50
175 #define AR7240_STATS_TXBROAD 0x54
176 #define AR7240_STATS_TXPAUSE 0x58
177 #define AR7240_STATS_TXMULTI 0x5c
178 #define AR7240_STATS_TXUNDERRUN 0x60
179 #define AR7240_STATS_TX64BYTE 0x64
180 #define AR7240_STATS_TX128BYTE 0x68
181 #define AR7240_STATS_TX256BYTE 0x6c
182 #define AR7240_STATS_TX512BYTE 0x70
183 #define AR7240_STATS_TX1024BYTE 0x74
184 #define AR7240_STATS_TX1518BYTE 0x78
185 #define AR7240_STATS_TXMAXBYTE 0x7c
186 #define AR7240_STATS_TXOVERSIZE 0x80
187 #define AR7240_STATS_TXBYTE 0x84
188 #define AR7240_STATS_TXCOLLISION 0x8c
189 #define AR7240_STATS_TXABORTCOL 0x90
190 #define AR7240_STATS_TXMULTICOL 0x94
191 #define AR7240_STATS_TXSINGLECOL 0x98
192 #define AR7240_STATS_TXEXCDEFER 0x9c
193 #define AR7240_STATS_TXDEFER 0xa0
194 #define AR7240_STATS_TXLATECOL 0xa4
195  
196 #define AR7240_PORT_CPU 0
197 #define AR7240_NUM_PORTS 6
198 #define AR7240_NUM_PHYS 5
199  
200 #define AR7240_PHY_ID1 0x004d
201 #define AR7240_PHY_ID2 0xd041
202  
203 #define AR934X_PHY_ID1 0x004d
204 #define AR934X_PHY_ID2 0xd042
205  
206 #define AR7240_MAX_VLANS 16
207  
208 #define AR934X_REG_OPER_MODE0 0x04
209 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
210 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
211  
212 #define AR934X_REG_OPER_MODE1 0x08
213 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
214  
215 #define AR934X_REG_FLOOD_MASK 0x2c
216 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
217 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
218  
219 #define AR934X_REG_QM_CTRL 0x3c
220 #define AR934X_QM_CTRL_ARP_EN BIT(15)
221  
222 #define AR934X_REG_AT_CTRL 0x5c
223 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
224 #define AR934X_AT_CTRL_AGE_EN BIT(17)
225 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
226  
227 #define AR934X_MIB_ENABLE BIT(30)
228  
229 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
230  
231 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
232 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
233 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
234 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
235 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
236 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
237 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
238 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
239 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
240  
241 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
242 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
243 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
244 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
245 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
246 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
247 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
248  
249 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
250  
251 struct ar7240sw_port_stat {
252 unsigned long rx_broadcast;
253 unsigned long rx_pause;
254 unsigned long rx_multicast;
255 unsigned long rx_fcs_error;
256 unsigned long rx_align_error;
257 unsigned long rx_runt;
258 unsigned long rx_fragments;
259 unsigned long rx_64byte;
260 unsigned long rx_128byte;
261 unsigned long rx_256byte;
262 unsigned long rx_512byte;
263 unsigned long rx_1024byte;
264 unsigned long rx_1518byte;
265 unsigned long rx_maxbyte;
266 unsigned long rx_toolong;
267 unsigned long rx_good_byte;
268 unsigned long rx_bad_byte;
269 unsigned long rx_overflow;
270 unsigned long filtered;
271  
272 unsigned long tx_broadcast;
273 unsigned long tx_pause;
274 unsigned long tx_multicast;
275 unsigned long tx_underrun;
276 unsigned long tx_64byte;
277 unsigned long tx_128byte;
278 unsigned long tx_256byte;
279 unsigned long tx_512byte;
280 unsigned long tx_1024byte;
281 unsigned long tx_1518byte;
282 unsigned long tx_maxbyte;
283 unsigned long tx_oversize;
284 unsigned long tx_byte;
285 unsigned long tx_collision;
286 unsigned long tx_abortcol;
287 unsigned long tx_multicol;
288 unsigned long tx_singlecol;
289 unsigned long tx_excdefer;
290 unsigned long tx_defer;
291 unsigned long tx_xlatecol;
292 };
293  
294 struct ar7240sw {
295 struct mii_bus *mii_bus;
296 struct mii_bus *switch_mii_bus;
297 struct device_node *of_node;
298 struct device_node *mdio_node;
299 struct switch_dev swdev;
300 int num_ports;
301 u8 ver;
302 bool vlan;
303 u16 vlan_id[AR7240_MAX_VLANS];
304 u8 vlan_table[AR7240_MAX_VLANS];
305 u8 vlan_tagged;
306 u16 pvid[AR7240_NUM_PORTS];
307 char buf[80];
308  
309 rwlock_t stats_lock;
310 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
311 };
312  
313 struct ar7240sw_hw_stat {
314 char string[ETH_GSTRING_LEN];
315 int sizeof_stat;
316 int reg;
317 };
318  
319 static DEFINE_MUTEX(reg_mutex);
320  
321 static inline int sw_is_ar7240(struct ar7240sw *as)
322 {
323 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
324 }
325  
326 static inline int sw_is_ar934x(struct ar7240sw *as)
327 {
328 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
329 }
330  
331 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
332 {
333 return BIT(port);
334 }
335  
336 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
337 {
338 return BIT(as->swdev.ports) - 1;
339 }
340  
341 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
342 {
343 return ar7240sw_port_mask_all(as) & ~BIT(port);
344 }
345  
346 static inline u16 mk_phy_addr(u32 reg)
347 {
348 return 0x17 & ((reg >> 4) | 0x10);
349 }
350  
351 static inline u16 mk_phy_reg(u32 reg)
352 {
353 return (reg << 1) & 0x1e;
354 }
355  
356 static inline u16 mk_high_addr(u32 reg)
357 {
358 return (reg >> 7) & 0x1ff;
359 }
360  
361 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
362 {
363 unsigned long flags;
364 u16 phy_addr;
365 u16 phy_reg;
366 u32 hi, lo;
367  
368 reg = (reg & 0xfffffffc) >> 2;
369 phy_addr = mk_phy_addr(reg);
370 phy_reg = mk_phy_reg(reg);
371  
372 local_irq_save(flags);
373 mutex_lock(&mii->mdio_lock);
374 mii->write(mii, 0x1f, 0x10, mk_high_addr(reg));
375 lo = (u32) mii->read(mii, phy_addr, phy_reg);
376 hi = (u32) mii->read(mii, phy_addr, phy_reg + 1);
377 mutex_unlock(&mii->mdio_lock);
378 local_irq_restore(flags);
379  
380 return (hi << 16) | lo;
381 }
382  
383 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
384 {
385 unsigned long flags;
386 u16 phy_addr;
387 u16 phy_reg;
388  
389 reg = (reg & 0xfffffffc) >> 2;
390 phy_addr = mk_phy_addr(reg);
391 phy_reg = mk_phy_reg(reg);
392  
393 local_irq_save(flags);
394 mutex_lock(&mii->mdio_lock);
395 mii->write(mii, 0x1f, 0x10, mk_high_addr(reg));
396 mii->write(mii, phy_addr, phy_reg + 1, (val >> 16));
397 mii->write(mii, phy_addr, phy_reg, (val & 0xffff));
398 mutex_unlock(&mii->mdio_lock);
399 local_irq_restore(flags);
400 }
401  
402 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
403 {
404 u32 ret;
405  
406 mutex_lock(&reg_mutex);
407 ret = __ar7240sw_reg_read(mii, reg_addr);
408 mutex_unlock(&reg_mutex);
409  
410 return ret;
411 }
412  
413 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
414 {
415 mutex_lock(&reg_mutex);
416 __ar7240sw_reg_write(mii, reg_addr, reg_val);
417 mutex_unlock(&reg_mutex);
418 }
419  
420 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
421 {
422 u32 t;
423  
424 mutex_lock(&reg_mutex);
425 t = __ar7240sw_reg_read(mii, reg);
426 t &= ~mask;
427 t |= val;
428 __ar7240sw_reg_write(mii, reg, t);
429 mutex_unlock(&reg_mutex);
430  
431 return t;
432 }
433  
434 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
435 {
436 u32 t;
437  
438 mutex_lock(&reg_mutex);
439 t = __ar7240sw_reg_read(mii, reg);
440 t |= val;
441 __ar7240sw_reg_write(mii, reg, t);
442 mutex_unlock(&reg_mutex);
443 }
444  
445 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
446 unsigned timeout)
447 {
448 int i;
449  
450 for (i = 0; i < timeout; i++) {
451 u32 t;
452  
453 t = __ar7240sw_reg_read(mii, reg);
454 if ((t & mask) == val)
455 return 0;
456  
457 usleep_range(1000, 2000);
458 }
459  
460 return -ETIMEDOUT;
461 }
462  
463 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
464 unsigned timeout)
465 {
466 int ret;
467  
468 mutex_lock(&reg_mutex);
469 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
470 mutex_unlock(&reg_mutex);
471 return ret;
472 }
473  
474 int ar7240sw_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
475 {
476 u32 t, val = 0xffff;
477 int err;
478 struct ar7240sw *as = bus->priv;
479 struct mii_bus *mii = as->mii_bus;
480  
481 if (phy_addr >= AR7240_NUM_PHYS)
482 return 0xffff;
483  
484 mutex_lock(&reg_mutex);
485 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
486 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
487 AR7240_MDIO_CTRL_MASTER_EN |
488 AR7240_MDIO_CTRL_BUSY |
489 AR7240_MDIO_CTRL_CMD_READ;
490  
491 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
492 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
493 AR7240_MDIO_CTRL_BUSY, 0, 5);
494 if (!err)
495 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
496 mutex_unlock(&reg_mutex);
497  
498 return val & AR7240_MDIO_CTRL_DATA_M;
499 }
500  
501 int ar7240sw_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
502 u16 reg_val)
503 {
504 u32 t;
505 int ret;
506 struct ar7240sw *as = bus->priv;
507 struct mii_bus *mii = as->mii_bus;
508  
509 if (phy_addr >= AR7240_NUM_PHYS)
510 return -EINVAL;
511  
512 mutex_lock(&reg_mutex);
513 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
514 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
515 AR7240_MDIO_CTRL_MASTER_EN |
516 AR7240_MDIO_CTRL_BUSY |
517 AR7240_MDIO_CTRL_CMD_WRITE |
518 reg_val;
519  
520 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
521 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
522 AR7240_MDIO_CTRL_BUSY, 0, 5);
523 mutex_unlock(&reg_mutex);
524  
525 return ret;
526 }
527  
528 static int ar7240sw_capture_stats(struct ar7240sw *as)
529 {
530 struct mii_bus *mii = as->mii_bus;
531 int port;
532 int ret;
533  
534 write_lock(&as->stats_lock);
535  
536 /* Capture the hardware statistics for all ports */
537 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
538 (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
539 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
540  
541 /* Wait for the capturing to complete. */
542 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
543 AR7240_MIB_BUSY, 0, 10);
544  
545 if (ret)
546 goto unlock;
547  
548 for (port = 0; port < AR7240_NUM_PORTS; port++) {
549 unsigned int base;
550 struct ar7240sw_port_stat *stats;
551  
552 base = AR7240_REG_STATS_BASE(port);
553 stats = &as->port_stats[port];
554  
555 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
556  
557 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
558 stats->tx_byte += READ_STAT(TXBYTE);
559  
560 #undef READ_STAT
561 }
562  
563 ret = 0;
564  
565 unlock:
566 write_unlock(&as->stats_lock);
567 return ret;
568 }
569  
570 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
571 {
572 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
573 AR7240_PORT_CTRL_STATE_DISABLED);
574 }
575  
576 static void ar7240sw_setup(struct ar7240sw *as)
577 {
578 struct mii_bus *mii = as->mii_bus;
579  
580 /* Enable CPU port, and disable mirror port */
581 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
582 AR7240_CPU_PORT_EN |
583 (15 << AR7240_MIRROR_PORT_S));
584  
585 /* Setup TAG priority mapping */
586 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
587  
588 if (sw_is_ar934x(as)) {
589 /* Enable aging, MAC replacing */
590 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
591 0x2b /* 5 min age time */ |
592 AR934X_AT_CTRL_AGE_EN |
593 AR934X_AT_CTRL_LEARN_CHANGE);
594 /* Enable ARP frame acknowledge */
595 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
596 AR934X_QM_CTRL_ARP_EN);
597 /* Enable Broadcast/Multicast frames transmitted to the CPU */
598 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
599 AR934X_FLOOD_MASK_BC_DP(0) |
600 AR934X_FLOOD_MASK_MC_DP(0));
601  
602 /* setup MTU */
603 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
604 AR9340_GLOBAL_CTRL_MTU_M,
605 AR9340_GLOBAL_CTRL_MTU_M);
606  
607 /* Enable MIB counters */
608 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
609 AR934X_MIB_ENABLE);
610  
611 } else {
612 /* Enable ARP frame acknowledge, aging, MAC replacing */
613 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
614 AR7240_AT_CTRL_RESERVED |
615 0x2b /* 5 min age time */ |
616 AR7240_AT_CTRL_AGE_EN |
617 AR7240_AT_CTRL_ARP_EN |
618 AR7240_AT_CTRL_LEARN_CHANGE);
619 /* Enable Broadcast frames transmitted to the CPU */
620 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
621 AR7240_FLOOD_MASK_BROAD_TO_CPU);
622  
623 /* setup MTU */
624 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
625 AR7240_GLOBAL_CTRL_MTU_M,
626 AR7240_GLOBAL_CTRL_MTU_M);
627 }
628  
629 /* setup Service TAG */
630 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
631 }
632  
633 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
634 static int
635 ar7240sw_phy_poll_reset(struct mii_bus *bus)
636 {
637 const unsigned int sleep_msecs = 20;
638 int ret, elapsed, i;
639  
640 for (elapsed = sleep_msecs; elapsed <= 600;
641 elapsed += sleep_msecs) {
642 msleep(sleep_msecs);
643 for (i = 0; i < AR7240_NUM_PHYS; i++) {
644 ret = ar7240sw_phy_read(bus, i, MII_BMCR);
645 if (ret < 0)
646 return ret;
647 if (ret & BMCR_RESET)
648 break;
649 if (i == AR7240_NUM_PHYS - 1) {
650 usleep_range(1000, 2000);
651 return 0;
652 }
653 }
654 }
655 return -ETIMEDOUT;
656 }
657  
658 static int ar7240sw_reset(struct ar7240sw *as)
659 {
660 struct mii_bus *mii = as->mii_bus;
661 struct mii_bus *swmii = as->switch_mii_bus;
662 int ret;
663 int i;
664  
665 /* Set all ports to disabled state. */
666 for (i = 0; i < AR7240_NUM_PORTS; i++)
667 ar7240sw_disable_port(as, i);
668  
669 /* Wait for transmit queues to drain. */
670 usleep_range(2000, 3000);
671  
672 /* Reset the switch. */
673 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
674 AR7240_MASK_CTRL_SOFT_RESET);
675  
676 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
677 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
678  
679 /* setup PHYs */
680 for (i = 0; i < AR7240_NUM_PHYS; i++) {
681 ar7240sw_phy_write(swmii, i, MII_ADVERTISE,
682 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
683 ADVERTISE_PAUSE_ASYM);
684 ar7240sw_phy_write(swmii, i, MII_BMCR,
685 BMCR_RESET | BMCR_ANENABLE);
686 }
687 ret = ar7240sw_phy_poll_reset(swmii);
688 if (ret)
689 return ret;
690  
691 ar7240sw_setup(as);
692 return ret;
693 }
694  
695 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
696 {
697 struct mii_bus *mii = as->mii_bus;
698 u32 ctrl;
699 u32 vid, mode;
700  
701 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
702 AR7240_PORT_CTRL_SINGLE_VLAN;
703  
704 if (port == AR7240_PORT_CPU) {
705 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
706 AR7240_PORT_STATUS_SPEED_1000 |
707 AR7240_PORT_STATUS_TXFLOW |
708 AR7240_PORT_STATUS_RXFLOW |
709 AR7240_PORT_STATUS_TXMAC |
710 AR7240_PORT_STATUS_RXMAC |
711 AR7240_PORT_STATUS_DUPLEX);
712 } else {
713 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
714 AR7240_PORT_STATUS_LINK_AUTO);
715 }
716  
717 /* Set the default VID for this port */
718 if (as->vlan) {
719 vid = as->vlan_id[as->pvid[port]];
720 mode = AR7240_PORT_VLAN_MODE_SECURE;
721 } else {
722 vid = port;
723 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
724 }
725  
726 if (as->vlan) {
727 if (as->vlan_tagged & BIT(port))
728 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
729 AR7240_PORT_CTRL_VLAN_MODE_S;
730 else
731 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
732 AR7240_PORT_CTRL_VLAN_MODE_S;
733 } else {
734 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
735 AR7240_PORT_CTRL_VLAN_MODE_S;
736 }
737  
738 if (!portmask) {
739 if (port == AR7240_PORT_CPU)
740 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
741 else
742 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
743 }
744  
745 /* preserve mirror rx&tx flags */
746 ctrl |= ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port)) &
747 (AR7240_PORT_CTRL_MIRROR_RX | AR7240_PORT_CTRL_MIRROR_TX);
748  
749 /* allow the port to talk to all other ports, but exclude its
750 * own ID to prevent frames from being reflected back to the
751 * port that they came from */
752 portmask &= ar7240sw_port_mask_but(as, port);
753  
754 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
755 if (sw_is_ar934x(as)) {
756 u32 vlan1, vlan2;
757  
758 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
759 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
760 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
761 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
762 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
763 } else {
764 u32 vlan;
765  
766 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
767 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
768  
769 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
770 }
771 }
772  
773 static int
774 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
775 struct switch_val *val)
776 {
777 struct ar7240sw *as = sw_to_ar7240(dev);
778 as->vlan_id[val->port_vlan] = val->value.i;
779 return 0;
780 }
781  
782 static int
783 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
784 struct switch_val *val)
785 {
786 struct ar7240sw *as = sw_to_ar7240(dev);
787 val->value.i = as->vlan_id[val->port_vlan];
788 return 0;
789 }
790  
791 static int
792 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
793 {
794 struct ar7240sw *as = sw_to_ar7240(dev);
795  
796 /* make sure no invalid PVIDs get set */
797  
798 if (vlan >= dev->vlans)
799 return -EINVAL;
800  
801 as->pvid[port] = vlan;
802 return 0;
803 }
804  
805 static int
806 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
807 {
808 struct ar7240sw *as = sw_to_ar7240(dev);
809 *vlan = as->pvid[port];
810 return 0;
811 }
812  
813 static int
814 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
815 {
816 struct ar7240sw *as = sw_to_ar7240(dev);
817 u8 ports = as->vlan_table[val->port_vlan];
818 int i;
819  
820 val->len = 0;
821 for (i = 0; i < as->swdev.ports; i++) {
822 struct switch_port *p;
823  
824 if (!(ports & (1 << i)))
825 continue;
826  
827 p = &val->value.ports[val->len++];
828 p->id = i;
829 if (as->vlan_tagged & (1 << i))
830 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
831 else
832 p->flags = 0;
833 }
834 return 0;
835 }
836  
837 static int
838 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
839 {
840 struct ar7240sw *as = sw_to_ar7240(dev);
841 u8 *vt = &as->vlan_table[val->port_vlan];
842 int i, j;
843  
844 *vt = 0;
845 for (i = 0; i < val->len; i++) {
846 struct switch_port *p = &val->value.ports[i];
847  
848 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
849 as->vlan_tagged |= (1 << p->id);
850 else {
851 as->vlan_tagged &= ~(1 << p->id);
852 as->pvid[p->id] = val->port_vlan;
853  
854 /* make sure that an untagged port does not
855 * appear in other vlans */
856 for (j = 0; j < AR7240_MAX_VLANS; j++) {
857 if (j == val->port_vlan)
858 continue;
859 as->vlan_table[j] &= ~(1 << p->id);
860 }
861 }
862  
863 *vt |= 1 << p->id;
864 }
865 return 0;
866 }
867  
868 static int
869 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
870 struct switch_val *val)
871 {
872 struct ar7240sw *as = sw_to_ar7240(dev);
873 as->vlan = !!val->value.i;
874 return 0;
875 }
876  
877 static int
878 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
879 struct switch_val *val)
880 {
881 struct ar7240sw *as = sw_to_ar7240(dev);
882 val->value.i = as->vlan;
883 return 0;
884 }
885  
886 static void
887 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
888 {
889 struct mii_bus *mii = as->mii_bus;
890  
891 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
892 return;
893  
894 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
895 val &= AR7240_VTUDATA_MEMBER;
896 val |= AR7240_VTUDATA_VALID;
897 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
898 }
899 op |= AR7240_VTU_ACTIVE;
900 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
901 }
902  
903 static int
904 ar7240_hw_apply(struct switch_dev *dev)
905 {
906 struct ar7240sw *as = sw_to_ar7240(dev);
907 u8 portmask[AR7240_NUM_PORTS];
908 int i, j;
909  
910 /* flush all vlan translation unit entries */
911 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
912  
913 memset(portmask, 0, sizeof(portmask));
914 if (as->vlan) {
915 /* calculate the port destination masks and load vlans
916 * into the vlan translation unit */
917 for (j = 0; j < AR7240_MAX_VLANS; j++) {
918 u8 vp = as->vlan_table[j];
919  
920 if (!vp)
921 continue;
922  
923 for (i = 0; i < as->swdev.ports; i++) {
924 u8 mask = (1 << i);
925 if (vp & mask)
926 portmask[i] |= vp & ~mask;
927 }
928  
929 ar7240_vtu_op(as,
930 AR7240_VTU_OP_LOAD |
931 (as->vlan_id[j] << AR7240_VTU_VID_S),
932 as->vlan_table[j]);
933 }
934 } else {
935 /* vlan disabled:
936 * isolate all ports, but connect them to the cpu port */
937 for (i = 0; i < as->swdev.ports; i++) {
938 if (i == AR7240_PORT_CPU)
939 continue;
940  
941 portmask[i] = 1 << AR7240_PORT_CPU;
942 portmask[AR7240_PORT_CPU] |= (1 << i);
943 }
944 }
945  
946 /* update the port destination mask registers and tag settings */
947 for (i = 0; i < as->swdev.ports; i++)
948 ar7240sw_setup_port(as, i, portmask[i]);
949  
950 return 0;
951 }
952  
953 static int
954 ar7240_reset_switch(struct switch_dev *dev)
955 {
956 struct ar7240sw *as = sw_to_ar7240(dev);
957 ar7240sw_reset(as);
958 return 0;
959 }
960  
961 static int
962 ar7240_get_port_link(struct switch_dev *dev, int port,
963 struct switch_port_link *link)
964 {
965 struct ar7240sw *as = sw_to_ar7240(dev);
966 struct mii_bus *mii = as->mii_bus;
967 u32 status;
968  
969 if (port >= AR7240_NUM_PORTS)
970 return -EINVAL;
971  
972 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
973 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
974 if (link->aneg) {
975 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
976 if (!link->link)
977 return 0;
978 } else {
979 link->link = true;
980 }
981  
982 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
983 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
984 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
985 switch (status & AR7240_PORT_STATUS_SPEED_M) {
986 case AR7240_PORT_STATUS_SPEED_10:
987 link->speed = SWITCH_PORT_SPEED_10;
988 break;
989 case AR7240_PORT_STATUS_SPEED_100:
990 link->speed = SWITCH_PORT_SPEED_100;
991 break;
992 case AR7240_PORT_STATUS_SPEED_1000:
993 link->speed = SWITCH_PORT_SPEED_1000;
994 break;
995 }
996  
997 return 0;
998 }
999  
1000 static int
1001 ar7240_get_port_stats(struct switch_dev *dev, int port,
1002 struct switch_port_stats *stats)
1003 {
1004 struct ar7240sw *as = sw_to_ar7240(dev);
1005  
1006 if (port >= AR7240_NUM_PORTS)
1007 return -EINVAL;
1008  
1009 ar7240sw_capture_stats(as);
1010  
1011 read_lock(&as->stats_lock);
1012 stats->rx_bytes = as->port_stats[port].rx_good_byte;
1013 stats->tx_bytes = as->port_stats[port].tx_byte;
1014 read_unlock(&as->stats_lock);
1015  
1016 return 0;
1017 }
1018  
1019 static int
1020 ar7240_set_mirror_monitor_port(struct switch_dev *dev,
1021 const struct switch_attr *attr,
1022 struct switch_val *val)
1023 {
1024 struct ar7240sw *as = sw_to_ar7240(dev);
1025 struct mii_bus *mii = as->mii_bus;
1026  
1027 int port = val->value.i;
1028  
1029 if (port > 15)
1030 return -EINVAL;
1031  
1032 ar7240sw_reg_rmw(mii, AR7240_REG_CPU_PORT,
1033 AR7240_MIRROR_PORT_M << AR7240_MIRROR_PORT_S,
1034 port << AR7240_MIRROR_PORT_S);
1035  
1036 return 0;
1037 }
1038  
1039 static int
1040 ar7240_get_mirror_monitor_port(struct switch_dev *dev,
1041 const struct switch_attr *attr,
1042 struct switch_val *val)
1043 {
1044 struct ar7240sw *as = sw_to_ar7240(dev);
1045 struct mii_bus *mii = as->mii_bus;
1046  
1047 u32 ret;
1048  
1049 ret = ar7240sw_reg_read(mii, AR7240_REG_CPU_PORT);
1050 val->value.i = (ret >> AR7240_MIRROR_PORT_S) & AR7240_MIRROR_PORT_M;
1051  
1052 return 0;
1053 }
1054  
1055 static int
1056 ar7240_set_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1057 struct switch_val *val)
1058 {
1059 struct ar7240sw *as = sw_to_ar7240(dev);
1060 struct mii_bus *mii = as->mii_bus;
1061  
1062 int port = val->port_vlan;
1063  
1064 if (port >= dev->ports)
1065 return -EINVAL;
1066  
1067 if (val && val->value.i == 1)
1068 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1069 AR7240_PORT_CTRL_MIRROR_RX);
1070 else
1071 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1072 AR7240_PORT_CTRL_MIRROR_RX, 0);
1073  
1074 return 0;
1075 }
1076  
1077 static int
1078 ar7240_get_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1079 struct switch_val *val)
1080 {
1081 struct ar7240sw *as = sw_to_ar7240(dev);
1082 struct mii_bus *mii = as->mii_bus;
1083  
1084 u32 ctrl;
1085  
1086 int port = val->port_vlan;
1087  
1088 if (port >= dev->ports)
1089 return -EINVAL;
1090  
1091 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1092  
1093 if ((ctrl & AR7240_PORT_CTRL_MIRROR_RX) == AR7240_PORT_CTRL_MIRROR_RX)
1094 val->value.i = 1;
1095 else
1096 val->value.i = 0;
1097  
1098 return 0;
1099 }
1100  
1101 static int
1102 ar7240_set_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1103 struct switch_val *val)
1104 {
1105 struct ar7240sw *as = sw_to_ar7240(dev);
1106 struct mii_bus *mii = as->mii_bus;
1107  
1108 int port = val->port_vlan;
1109  
1110 if (port >= dev->ports)
1111 return -EINVAL;
1112  
1113 if (val && val->value.i == 1)
1114 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1115 AR7240_PORT_CTRL_MIRROR_TX);
1116 else
1117 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1118 AR7240_PORT_CTRL_MIRROR_TX, 0);
1119  
1120 return 0;
1121 }
1122  
1123 static int
1124 ar7240_get_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1125 struct switch_val *val)
1126 {
1127 struct ar7240sw *as = sw_to_ar7240(dev);
1128 struct mii_bus *mii = as->mii_bus;
1129  
1130 u32 ctrl;
1131  
1132 int port = val->port_vlan;
1133  
1134 if (port >= dev->ports)
1135 return -EINVAL;
1136  
1137 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1138  
1139 if ((ctrl & AR7240_PORT_CTRL_MIRROR_TX) == AR7240_PORT_CTRL_MIRROR_TX)
1140 val->value.i = 1;
1141 else
1142 val->value.i = 0;
1143  
1144 return 0;
1145 }
1146  
1147 static struct switch_attr ar7240_globals[] = {
1148 {
1149 .type = SWITCH_TYPE_INT,
1150 .name = "enable_vlan",
1151 .description = "Enable VLAN mode",
1152 .set = ar7240_set_vlan,
1153 .get = ar7240_get_vlan,
1154 .max = 1
1155 },
1156 {
1157 .type = SWITCH_TYPE_INT,
1158 .name = "mirror_monitor_port",
1159 .description = "Mirror monitor port",
1160 .set = ar7240_set_mirror_monitor_port,
1161 .get = ar7240_get_mirror_monitor_port,
1162 .max = 15
1163 },
1164 };
1165  
1166 static struct switch_attr ar7240_port[] = {
1167 {
1168 .type = SWITCH_TYPE_INT,
1169 .name = "enable_mirror_rx",
1170 .description = "Enable mirroring of RX packets",
1171 .set = ar7240_set_mirror_rx,
1172 .get = ar7240_get_mirror_rx,
1173 .max = 1
1174 },
1175 {
1176 .type = SWITCH_TYPE_INT,
1177 .name = "enable_mirror_tx",
1178 .description = "Enable mirroring of TX packets",
1179 .set = ar7240_set_mirror_tx,
1180 .get = ar7240_get_mirror_tx,
1181 .max = 1
1182 },
1183 };
1184  
1185 static struct switch_attr ar7240_vlan[] = {
1186 {
1187 .type = SWITCH_TYPE_INT,
1188 .name = "vid",
1189 .description = "VLAN ID",
1190 .set = ar7240_set_vid,
1191 .get = ar7240_get_vid,
1192 .max = 4094,
1193 },
1194 };
1195  
1196 static const struct switch_dev_ops ar7240_ops = {
1197 .attr_global = {
1198 .attr = ar7240_globals,
1199 .n_attr = ARRAY_SIZE(ar7240_globals),
1200 },
1201 .attr_port = {
1202 .attr = ar7240_port,
1203 .n_attr = ARRAY_SIZE(ar7240_port),
1204 },
1205 .attr_vlan = {
1206 .attr = ar7240_vlan,
1207 .n_attr = ARRAY_SIZE(ar7240_vlan),
1208 },
1209 .get_port_pvid = ar7240_get_pvid,
1210 .set_port_pvid = ar7240_set_pvid,
1211 .get_vlan_ports = ar7240_get_ports,
1212 .set_vlan_ports = ar7240_set_ports,
1213 .apply_config = ar7240_hw_apply,
1214 .reset_switch = ar7240_reset_switch,
1215 .get_port_link = ar7240_get_port_link,
1216 .get_port_stats = ar7240_get_port_stats,
1217 };
1218  
1219 static int
1220 ag71xx_ar7240_probe(struct mdio_device *mdiodev)
1221 {
1222 struct mii_bus *mii = mdiodev->bus;
1223 struct ar7240sw *as;
1224 struct switch_dev *swdev;
1225 struct reset_control *switch_reset;
1226 u32 ctrl;
1227 int phy_if_mode, err, i;
1228  
1229 as = devm_kzalloc(&mdiodev->dev, sizeof(*as), GFP_KERNEL);
1230 if (!as)
1231 return -ENOMEM;
1232  
1233 as->mii_bus = mii;
1234 as->of_node = mdiodev->dev.of_node;
1235 as->mdio_node = of_get_child_by_name(as->of_node, "mdio-bus");
1236  
1237 swdev = &as->swdev;
1238  
1239 switch_reset = devm_reset_control_get_optional(&mdiodev->dev, "switch");
1240 if (switch_reset) {
1241 reset_control_assert(switch_reset);
1242 msleep(50);
1243 reset_control_deassert(switch_reset);
1244 msleep(200);
1245 }
1246  
1247 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1248 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1249 AR7240_MASK_CTRL_VERSION_M;
1250  
1251 if (sw_is_ar7240(as)) {
1252 swdev->name = "AR7240/AR9330 built-in switch";
1253 swdev->ports = AR7240_NUM_PORTS - 1;
1254 } else if (sw_is_ar934x(as)) {
1255 swdev->name = "AR934X built-in switch";
1256 phy_if_mode = of_get_phy_mode(as->of_node);
1257  
1258 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1259 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1260 AR934X_OPER_MODE0_MAC_GMII_EN);
1261 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
1262 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1263 AR934X_OPER_MODE0_PHY_MII_EN);
1264 } else {
1265 pr_err("%s: invalid PHY interface mode\n",
1266 dev_name(&mdiodev->dev));
1267 return -EINVAL;
1268 }
1269  
1270 if (of_property_read_bool(as->of_node, "phy4-mii-enable")) {
1271 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1272 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1273 swdev->ports = AR7240_NUM_PORTS - 1;
1274 } else {
1275 swdev->ports = AR7240_NUM_PORTS;
1276 }
1277 } else {
1278 pr_err("%s: unsupported chip, ctrl=%08x\n",
1279 dev_name(&mdiodev->dev), ctrl);
1280 return -EINVAL;
1281 }
1282  
1283 swdev->cpu_port = AR7240_PORT_CPU;
1284 swdev->vlans = AR7240_MAX_VLANS;
1285 swdev->ops = &ar7240_ops;
1286 swdev->alias = dev_name(&mdiodev->dev);
1287  
1288 if ((err = register_switch(&as->swdev, NULL)) < 0)
1289 return err;
1290  
1291 pr_info("%s: Found an %s\n", dev_name(&mdiodev->dev), swdev->name);
1292  
1293 as->switch_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
1294 as->switch_mii_bus->name = "ar7240sw_mdio";
1295 as->switch_mii_bus->read = ar7240sw_phy_read;
1296 as->switch_mii_bus->write = ar7240sw_phy_write;
1297 as->switch_mii_bus->priv = as;
1298 as->switch_mii_bus->parent = &mdiodev->dev;
1299 snprintf(as->switch_mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&mdiodev->dev));
1300  
1301 if(as->mdio_node) {
1302 err = of_mdiobus_register(as->switch_mii_bus, as->mdio_node);
1303 if (err)
1304 return err;
1305 }
1306  
1307 /* initialize defaults */
1308 for (i = 0; i < AR7240_MAX_VLANS; i++)
1309 as->vlan_id[i] = i;
1310  
1311 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1312 ar7240sw_reset(as);
1313 ar7240_hw_apply(&as->swdev);
1314 rwlock_init(&as->stats_lock);
1315 dev_set_drvdata(&mdiodev->dev, as);
1316 return 0;
1317 }
1318  
1319 static void
1320 ag71xx_ar7240_remove(struct mdio_device *mdiodev)
1321 {
1322 struct ar7240sw *as = dev_get_drvdata(&mdiodev->dev);
1323 if(as->mdio_node)
1324 mdiobus_unregister(as->switch_mii_bus);
1325 unregister_switch(&as->swdev);
1326 }
1327  
1328 static const struct of_device_id ag71xx_sw_of_match[] = {
1329 { .compatible = "qca,ar8216-builtin" },
1330 { .compatible = "qca,ar8229-builtin" },
1331 { /* sentinel */ },
1332 };
1333  
1334 static struct mdio_driver ag71xx_sw_driver = {
1335 .probe = ag71xx_ar7240_probe,
1336 .remove = ag71xx_ar7240_remove,
1337 .mdiodrv.driver = {
1338 .name = "ag71xx-switch",
1339 .of_match_table = ag71xx_sw_of_match,
1340 },
1341 };
1342  
1343 mdio_module_driver(ag71xx_sw_driver);
1344 MODULE_LICENSE("GPL");