OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | // SPDX-License-Identifier: GPL-2.0-or-later OR MIT |
2 | |||
3 | #include "ar934x.dtsi" |
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4 | |||
5 | / { |
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6 | compatible = "qca,ar9344"; |
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7 | }; |
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8 | |||
9 | &cpuintc { |
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10 | qca,ddr-wb-channel-interrupts = <3>, <4>, <5>; |
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11 | qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>, |
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12 | <&ddr_ctrl 1>; |
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13 | }; |
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14 | |||
15 | &rst { |
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16 | intc2: interrupt-controller { |
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17 | compatible = "qca,ar9340-intc"; |
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18 | |||
19 | interrupt-parent = <&cpuintc>; |
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20 | interrupts = <2>; |
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21 | |||
22 | interrupt-controller; |
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23 | #interrupt-cells = <1>; |
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24 | |||
25 | qca,int-status-addr = <0xac>; |
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26 | qca,pending-bits = <0xf>, /* wmac */ |
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27 | <0x1f0>; /* pcie rc1 */ |
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28 | |||
29 | qca,ddr-wb-channel-interrupts = <0>, <1>; |
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30 | qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>; |
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31 | }; |
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32 | }; |
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33 | |||
34 | &apb { |
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35 | pcie: pcie-controller@180c0000 { |
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36 | compatible = "qcom,ar9340-pci", "qcom,ar7240-pci"; |
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37 | #address-cells = <3>; |
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38 | #size-cells = <2>; |
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39 | bus-range = <0x0 0x0>; |
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40 | reg = <0x180c0000 0x1000>, /* CRP */ |
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41 | <0x180f0000 0x100>, /* CTRL */ |
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42 | <0x14000000 0x1000>; /* CFG */ |
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43 | reg-names = "crp_base", "ctrl_base", "cfg_base"; |
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44 | ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */ |
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45 | 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */ |
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46 | interrupt-parent = <&intc2>; |
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47 | interrupts = <1>; |
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48 | |||
49 | interrupt-controller; |
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50 | #interrupt-cells = <1>; |
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51 | |||
52 | interrupt-map-mask = <0 0 0 1>; |
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53 | interrupt-map = <0 0 0 0 &pcie 0>; |
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54 | |||
55 | status = "disabled"; |
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56 | }; |
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57 | }; |
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58 | |||
59 | &wmac { |
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60 | interrupt-parent = <&intc2>; |
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61 | interrupts = <0>; |
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62 | }; |