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1 office 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include <dt-bindings/clock/ath79-clk.h>
3 #include "ath79.dtsi"
4  
5 / {
6 compatible = "qca,ar7100";
7  
8 cpus {
9 #address-cells = <1>;
10 #size-cells = <0>;
11  
12 cpu@0 {
13 device_type = "cpu";
14 compatible = "mips,mips24Kc";
15 clocks = <&pll ATH79_CLK_CPU>;
16 reg = <0>;
17 };
18 };
19  
20 ahb {
21 apb {
22 ddr_ctrl: memory-controller@18000000 {
23 compatible = "qca,ar7100-ddr-controller";
24 reg = <0x18000000 0x100>;
25  
26 #qca,ddr-wb-channel-cells = <1>;
27 };
28  
29 uart: uart@18020000 {
30 compatible = "ns16550a";
31 reg = <0x18020000 0x20>;
32 interrupts = <3>;
33  
34 clocks = <&pll ATH79_CLK_AHB>;
35 clock-names = "uart";
36  
37 reg-io-width = <4>;
38 reg-shift = <2>;
39 no-loopback-test;
40  
41 status = "disabled";
42 };
43  
44 usb_phy: usb-phy@18030000 {
45 compatible = "qca,ar7100-usb-phy";
46 reg = <0x18030000 0x10>;
47  
48 reset-names = "usb-phy", "usb-host", "usb-ohci-dll";
49 resets = <&rst 4>, <&rst 5>, <&rst 6>;
50  
51 #phy-cells = <0>;
52  
53 status = "disabled";
54 };
55  
56 gpio: gpio@18040000 {
57 compatible = "qca,ar7100-gpio";
58 reg = <0x18040000 0x30>;
59 interrupts = <2>;
60  
61 ngpios = <16>;
62  
63 gpio-controller;
64 #gpio-cells = <2>;
65  
66 interrupt-controller;
67 #interrupt-cells = <2>;
68 };
69  
70 pll: pll-controller@18050000 {
71 compatible = "qca,ar7100-pll", "syscon";
72 reg = <0x18050000 0x20>;
73  
74 clock-names = "ref";
75 /* The board must provides the ref clock */
76  
77 #clock-cells = <1>;
78 clock-output-names = "cpu", "ddr", "ahb";
79 };
80  
81 wdt: wdt@18060008 {
82 compatible = "qca,ar7130-wdt";
83 reg = <0x18060008 0x8>;
84  
85 interrupts = <4>;
86  
87 clocks = <&pll ATH79_CLK_AHB>;
88 clock-names = "wdt";
89 };
90  
91 pci_intc: interrupt-controller@18060018 {
92 compatible = "qca,ar7100-misc-intc";
93 reg = <0x18060018 0x4>;
94 interrupt-parent = <&cpuintc>;
95 interrupts = <2>;
96 interrupt-controller;
97 #interrupt-cells = <1>;
98 };
99  
100 rst: reset-controller@18060024 {
101 compatible = "qca,ar7100-reset";
102 reg = <0x18060024 0x4>;
103  
104 #reset-cells = <1>;
105 };
106  
107 pcie0: pcie-controller@17010000 {
108 compatible = "qca,ar7100-pci";
109 #address-cells = <3>;
110 #size-cells = <2>;
111 bus-range = <0x0 0x0>;
112 reg = <0x17010000 0x100>;
113 reg-names = "cfg_base";
114 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000 /* pci memory */
115 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
116  
117 interrupt-parent = <&pci_intc>;
118 interrupts = <4>;
119  
120 #interrupt-cells = <1>;
121  
122 interrupt-map-mask = <0xf800 0 0 0>;
123 interrupt-map = <0x8800 0 0 0 &pci_intc 0
124 0x9000 0 0 0 &pci_intc 1
125 0x9800 0 0 0 &pci_intc 2>;
126  
127 status = "disabled";
128 };
129 };
130 };
131  
132 usb2: usb@1b000000 {
133 compatible = "generic-ehci";
134 reg = <0x1b000000 0x1000>;
135  
136 interrupt-parent = <&cpuintc>;
137 interrupts = <3>;
138  
139 phy-names = "usb-phy";
140 phys = <&usb_phy>;
141  
142 has-synopsys-hc-bug;
143  
144 status = "disabled";
145 };
146  
147 usb1: usb@1c000000 {
148 compatible = "generic-ohci";
149 reg = <0x1c000000 0x1000>;
150  
151 interrupt-parent = <&miscintc>;
152 interrupts = <6>;
153  
154 phy-names = "usb-phy";
155 phys = <&usb_phy>;
156  
157 status = "disabled";
158 };
159  
160 spi: spi@1f000000 {
161 compatible = "qca,ar7100-spi";
162 reg = <0x1f000000 0x10>;
163  
164 clocks = <&pll ATH79_CLK_AHB>;
165 clock-names = "ahb";
166  
167 #address-cells = <1>;
168 #size-cells = <0>;
169  
170 status = "disabled";
171 };
172 };
173  
174 &cpuintc {
175 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
176 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
177 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
178 };
179  
180 &miscintc {
181 compatible = "qca,ar7100-misc-intc";
182 };
183  
184 &eth0 {
185 compatible = "qca,ar7100-eth", "syscon";
186 reg = <0x19000000 0x200
187 0x18070000 0x4>;
188  
189 pll-data = <0x00110000 0x00001099 0x00991099>;
190 pll-reg = <0x4 0x10 17>;
191 pll-handle = <&pll>;
192 phy-mode = "rgmii";
193  
194 resets = <&rst 9>;
195 reset-names = "mac";
196 qca,mac-idx = <0>;
197 };
198  
199 &mdio1 {
200 builtin-switch;
201 };
202  
203 &eth1 {
204 compatible = "qca,ar7100-eth", "syscon";
205 reg = <0x1a000000 0x200
206 0x18070004 0x4>;
207  
208 pll-data = <0x00110000 0x00001099 0x00991099>;
209 pll-reg = <0x4 0x14 19>;
210 pll-handle = <&pll>;
211  
212 phy-mode = "rgmii";
213  
214 resets = <&rst 13>;
215 reset-names = "mac";
216 qca,mac-idx = <1>;
217 };