OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | --- a/arch/mips/ath79/common.h |
2 | +++ b/arch/mips/ath79/common.h |
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3 | @@ -28,6 +28,7 @@ void ath79_gpio_function_enable(u32 mask |
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4 | void ath79_gpio_function_disable(u32 mask); |
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5 | void ath79_gpio_function_setup(u32 set, u32 clear); |
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6 | void ath79_gpio_output_select(unsigned gpio, u8 val); |
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7 | +int ath79_gpio_direction_select(unsigned gpio, bool oe); |
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8 | void ath79_gpio_init(void); |
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9 | |||
10 | #endif /* __ATH79_COMMON_H */ |
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11 | --- a/arch/mips/ath79/gpio.c |
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12 | +++ b/arch/mips/ath79/gpio.c |
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13 | @@ -83,3 +83,19 @@ void __init ath79_gpio_output_select(uns |
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14 | /* flush write */ |
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15 | (void) __raw_readl(base + reg); |
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16 | } |
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17 | + |
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18 | +int ath79_gpio_direction_select(unsigned gpio, bool oe) |
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19 | +{ |
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20 | + void __iomem *base = ath79_gpio_base; |
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21 | + bool ieq_1 = (soc_is_ar934x() || |
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22 | + soc_is_qca953x()); |
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23 | + |
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24 | + if ((ieq_1 && oe) || (!ieq_1 && !oe)) |
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25 | + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio), |
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26 | + base + AR71XX_GPIO_REG_OE); |
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27 | + else |
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28 | + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio), |
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29 | + base + AR71XX_GPIO_REG_OE); |
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30 | + |
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31 | + return 0; |
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32 | +} |