OpenWrt – Blame information for rev 3
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | /* |
2 | * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips |
||
3 | * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org> |
||
4 | * |
||
5 | * This driver was base on: net/dsa/mv88e6060.c |
||
6 | * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips |
||
7 | * Copyright (c) 2008-2009 Marvell Semiconductor |
||
8 | * |
||
9 | * This program is free software; you can redistribute it and/or modify |
||
10 | * it under the terms of the GNU General Public License as published by |
||
11 | * the Free Software Foundation; either version 2 of the License, or |
||
12 | * (at your option) any later version. |
||
13 | */ |
||
14 | |||
15 | #include <linux/version.h> |
||
16 | #include <linux/list.h> |
||
17 | #include <linux/netdevice.h> |
||
18 | #include <linux/phy.h> |
||
19 | #include <net/dsa.h> |
||
20 | #include <linux/version.h> |
||
21 | |||
22 | #define REG_BASE 0x10 |
||
23 | #define REG_PHY(p) (REG_BASE + (p)) |
||
24 | #define REG_PORT(p) (REG_BASE + 8 + (p)) |
||
25 | #define REG_GLOBAL (REG_BASE + 0x0f) |
||
26 | #define NUM_PORTS 7 |
||
27 | |||
28 | static int reg_read(struct dsa_switch *ds, int addr, int reg) |
||
29 | { |
||
30 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) |
||
31 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
||
32 | return mdiobus_read(bus, addr, reg); |
||
33 | #else |
||
34 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->dev); |
||
35 | return mdiobus_read(bus, addr, reg); |
||
36 | #endif |
||
37 | } |
||
38 | |||
39 | #define REG_READ(addr, reg) \ |
||
40 | ({ \ |
||
41 | int __ret; \ |
||
42 | \ |
||
43 | __ret = reg_read(ds, addr, reg); \ |
||
44 | if (__ret < 0) \ |
||
45 | return __ret; \ |
||
46 | __ret; \ |
||
47 | }) |
||
48 | |||
49 | |||
50 | static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) |
||
51 | { |
||
52 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) |
||
53 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
||
54 | return mdiobus_write(bus, addr, reg, val); |
||
55 | #else |
||
56 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->dev); |
||
57 | return mdiobus_write(bus, addr, reg, val); |
||
58 | #endif |
||
59 | } |
||
60 | |||
61 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0) |
||
62 | static enum dsa_tag_protocol mv88e6063_get_tag_protocol(struct dsa_switch *ds) |
||
63 | { |
||
64 | return DSA_TAG_PROTO_TRAILER; |
||
65 | } |
||
66 | #endif |
||
67 | |||
68 | #define REG_WRITE(addr, reg, val) \ |
||
69 | ({ \ |
||
70 | int __ret; \ |
||
71 | \ |
||
72 | __ret = reg_write(ds, addr, reg, val); \ |
||
73 | if (__ret < 0) \ |
||
74 | return __ret; \ |
||
75 | }) |
||
76 | |||
77 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) |
||
78 | static char *mv88e6063_drv_probe(struct device *host_dev, int sw_addr) |
||
79 | #else |
||
80 | static const char *mv88e6063_drv_probe(struct device *dsa_dev, |
||
81 | struct device *host_dev, int sw_addr, |
||
82 | void **_priv) |
||
83 | #endif |
||
84 | { |
||
85 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev); |
||
86 | int ret; |
||
87 | |||
88 | if (!bus) |
||
89 | return NULL; |
||
90 | |||
91 | ret = mdiobus_read(bus, REG_PORT(0), 0x03); |
||
92 | if (ret >= 0) { |
||
93 | ret &= 0xfff0; |
||
94 | if (ret == 0x1530) |
||
95 | return "Marvell 88E6063"; |
||
96 | } |
||
97 | |||
98 | return NULL; |
||
99 | } |
||
100 | |||
101 | static int mv88e6063_switch_reset(struct dsa_switch *ds) |
||
102 | { |
||
103 | int i; |
||
104 | int ret; |
||
105 | |||
106 | /* |
||
107 | * Set all ports to the disabled state. |
||
108 | */ |
||
109 | for (i = 0; i < NUM_PORTS; i++) { |
||
110 | ret = REG_READ(REG_PORT(i), 0x04); |
||
111 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
||
112 | } |
||
113 | |||
114 | /* |
||
115 | * Wait for transmit queues to drain. |
||
116 | */ |
||
117 | msleep(2); |
||
118 | |||
119 | /* |
||
120 | * Reset the switch. |
||
121 | */ |
||
122 | REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); |
||
123 | |||
124 | /* |
||
125 | * Wait up to one second for reset to complete. |
||
126 | */ |
||
127 | for (i = 0; i < 1000; i++) { |
||
128 | ret = REG_READ(REG_GLOBAL, 0x00); |
||
129 | if ((ret & 0x8000) == 0x0000) |
||
130 | break; |
||
131 | |||
132 | msleep(1); |
||
133 | } |
||
134 | if (i == 1000) |
||
135 | return -ETIMEDOUT; |
||
136 | |||
137 | return 0; |
||
138 | } |
||
139 | |||
140 | static int mv88e6063_setup_global(struct dsa_switch *ds) |
||
141 | { |
||
142 | /* |
||
143 | * Disable discarding of frames with excessive collisions, |
||
144 | * set the maximum frame size to 1536 bytes, and mask all |
||
145 | * interrupt sources. |
||
146 | */ |
||
147 | REG_WRITE(REG_GLOBAL, 0x04, 0x0800); |
||
148 | |||
149 | /* |
||
150 | * Enable automatic address learning, set the address |
||
151 | * database size to 1024 entries, and set the default aging |
||
152 | * time to 5 minutes. |
||
153 | */ |
||
154 | REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); |
||
155 | |||
156 | return 0; |
||
157 | } |
||
158 | |||
159 | static int mv88e6063_setup_port(struct dsa_switch *ds, int p) |
||
160 | { |
||
161 | int addr = REG_PORT(p); |
||
162 | |||
163 | /* |
||
164 | * Do not force flow control, disable Ingress and Egress |
||
165 | * Header tagging, disable VLAN tunneling, and set the port |
||
166 | * state to Forwarding. Additionally, if this is the CPU |
||
167 | * port, enable Ingress and Egress Trailer tagging mode. |
||
168 | */ |
||
169 | REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); |
||
170 | |||
171 | /* |
||
172 | * Port based VLAN map: give each port its own address |
||
173 | * database, allow the CPU port to talk to each of the 'real' |
||
174 | * ports, and allow each of the 'real' ports to only talk to |
||
175 | * the CPU port. |
||
176 | */ |
||
177 | REG_WRITE(addr, 0x06, |
||
178 | ((p & 0xf) << 12) | |
||
179 | (dsa_is_cpu_port(ds, p) ? |
||
180 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,7,0) |
||
181 | ds->phys_port_mask : |
||
182 | #else |
||
183 | ds->enabled_port_mask : |
||
184 | #endif |
||
185 | (1 << ds->dst->cpu_port))); |
||
186 | |||
187 | /* |
||
188 | * Port Association Vector: when learning source addresses |
||
189 | * of packets, add the address to the address database using |
||
190 | * a port bitmap that has only the bit for this port set and |
||
191 | * the other bits clear. |
||
192 | */ |
||
193 | REG_WRITE(addr, 0x0b, 1 << p); |
||
194 | |||
195 | return 0; |
||
196 | } |
||
197 | |||
198 | static int mv88e6063_setup(struct dsa_switch *ds) |
||
199 | { |
||
200 | int i; |
||
201 | int ret; |
||
202 | |||
203 | ret = mv88e6063_switch_reset(ds); |
||
204 | if (ret < 0) |
||
205 | return ret; |
||
206 | |||
207 | /* @@@ initialise atu */ |
||
208 | |||
209 | ret = mv88e6063_setup_global(ds); |
||
210 | if (ret < 0) |
||
211 | return ret; |
||
212 | |||
213 | for (i = 0; i < NUM_PORTS; i++) { |
||
214 | ret = mv88e6063_setup_port(ds, i); |
||
215 | if (ret < 0) |
||
216 | return ret; |
||
217 | } |
||
218 | |||
219 | return 0; |
||
220 | } |
||
221 | |||
222 | static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) |
||
223 | { |
||
224 | REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); |
||
225 | REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); |
||
226 | REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); |
||
227 | |||
228 | return 0; |
||
229 | } |
||
230 | |||
231 | static int mv88e6063_port_to_phy_addr(int port) |
||
232 | { |
||
233 | if (port >= 0 && port <= NUM_PORTS) |
||
234 | return REG_PHY(port); |
||
235 | return -1; |
||
236 | } |
||
237 | |||
238 | static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) |
||
239 | { |
||
240 | int addr; |
||
241 | |||
242 | addr = mv88e6063_port_to_phy_addr(port); |
||
243 | if (addr == -1) |
||
244 | return 0xffff; |
||
245 | |||
246 | return reg_read(ds, addr, regnum); |
||
247 | } |
||
248 | |||
249 | static int |
||
250 | mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) |
||
251 | { |
||
252 | int addr; |
||
253 | |||
254 | addr = mv88e6063_port_to_phy_addr(port); |
||
255 | if (addr == -1) |
||
256 | return 0xffff; |
||
257 | |||
258 | return reg_write(ds, addr, regnum, val); |
||
259 | } |
||
260 | |||
261 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,9,0) |
||
262 | static struct dsa_switch_driver mv88e6063_switch_ops = { |
||
263 | #else |
||
264 | static struct dsa_switch_ops mv88e6063_switch_ops = { |
||
265 | #endif |
||
266 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,8,0) |
||
267 | .tag_protocol = htons(ETH_P_TRAILER), |
||
268 | #else |
||
269 | .get_tag_protocol = mv88e6063_get_tag_protocol, |
||
270 | #endif |
||
271 | .probe = mv88e6063_drv_probe, |
||
272 | .setup = mv88e6063_setup, |
||
273 | .set_addr = mv88e6063_set_addr, |
||
274 | .phy_read = mv88e6063_phy_read, |
||
275 | .phy_write = mv88e6063_phy_write, |
||
276 | }; |
||
277 | |||
278 | static int __init mv88e6063_init(void) |
||
279 | { |
||
280 | register_switch_driver(&mv88e6063_switch_ops); |
||
281 | return 0; |
||
282 | } |
||
283 | module_init(mv88e6063_init); |
||
284 | |||
285 | static void __exit mv88e6063_cleanup(void) |
||
286 | { |
||
287 | unregister_switch_driver(&mv88e6063_switch_ops); |
||
288 | } |
||
289 | module_exit(mv88e6063_cleanup); |