OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * NAND flash driver for the MikroTik RouterBOARD 91x series |
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3 | * |
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4 | * Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU General Public License version 2 as published |
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8 | * by the Free Software Foundation. |
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9 | */ |
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10 | |||
11 | #include <linux/kernel.h> |
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12 | #include <linux/spinlock.h> |
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13 | #include <linux/module.h> |
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14 | #include <linux/mtd/nand.h> |
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15 | #include <linux/mtd/mtd.h> |
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16 | #include <linux/mtd/partitions.h> |
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17 | #include <linux/platform_device.h> |
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18 | #include <linux/io.h> |
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19 | #include <linux/slab.h> |
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20 | #include <linux/gpio.h> |
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21 | #include <linux/platform_data/rb91x_nand.h> |
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3 | office | 22 | #include <linux/version.h> |
1 | office | 23 | |
24 | #include <asm/mach-ath79/ar71xx_regs.h> |
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25 | #include <asm/mach-ath79/ath79.h> |
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26 | |||
27 | #define DRV_DESC "NAND flash driver for the RouterBOARD 91x series" |
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28 | |||
29 | #define RB91X_NAND_NRWE BIT(12) |
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30 | |||
31 | #define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\ |
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32 | BIT(13) | BIT(14) | BIT(15)) |
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33 | |||
34 | #define RB91X_NAND_INPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY) |
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35 | #define RB91X_NAND_OUTPUT_BITS (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE) |
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36 | |||
37 | #define RB91X_NAND_LOW_DATA_MASK 0x1f |
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38 | #define RB91X_NAND_HIGH_DATA_MASK 0xe0 |
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39 | #define RB91X_NAND_HIGH_DATA_SHIFT 8 |
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40 | |||
41 | struct rb91x_nand_info { |
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42 | struct nand_chip chip; |
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43 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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44 | struct mtd_info mtd; |
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45 | #endif |
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46 | struct device *dev; |
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47 | |||
48 | int gpio_nce; |
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49 | int gpio_ale; |
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50 | int gpio_cle; |
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51 | int gpio_rdy; |
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52 | int gpio_read; |
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53 | int gpio_nrw; |
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54 | int gpio_nle; |
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55 | }; |
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56 | |||
57 | static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd) |
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58 | { |
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59 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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60 | return container_of(mtd, struct rb91x_nand_info, mtd); |
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61 | #else |
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62 | struct nand_chip *chip = mtd_to_nand(mtd); |
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63 | |||
64 | return container_of(chip, struct rb91x_nand_info, chip); |
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65 | #endif |
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66 | } |
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67 | |||
68 | static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc) |
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69 | { |
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70 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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71 | return &nfc->mtd; |
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72 | #else |
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73 | return nand_to_mtd(&nfc->chip); |
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74 | #endif |
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75 | } |
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76 | |||
77 | |||
78 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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79 | /* |
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80 | * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader |
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81 | * will not be able to find the kernel that we load. |
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82 | */ |
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83 | static struct nand_ecclayout rb91x_nand_ecclayout = { |
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84 | .eccbytes = 6, |
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85 | .eccpos = { 8, 9, 10, 13, 14, 15 }, |
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86 | .oobavail = 9, |
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87 | .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } |
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88 | }; |
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89 | |||
90 | #else |
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91 | |||
92 | static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section, |
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93 | struct mtd_oob_region *oobregion) |
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94 | { |
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95 | switch (section) { |
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96 | case 0: |
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97 | oobregion->offset = 8; |
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98 | oobregion->length = 3; |
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99 | return 0; |
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100 | case 1: |
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101 | oobregion->offset = 13; |
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102 | oobregion->length = 3; |
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103 | return 0; |
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104 | default: |
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105 | return -ERANGE; |
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106 | } |
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107 | } |
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108 | |||
109 | static int rb91x_ooblayout_free(struct mtd_info *mtd, int section, |
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110 | struct mtd_oob_region *oobregion) |
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111 | { |
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112 | switch (section) { |
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113 | case 0: |
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114 | oobregion->offset = 0; |
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115 | oobregion->length = 4; |
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116 | return 0; |
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117 | case 1: |
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118 | oobregion->offset = 4; |
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119 | oobregion->length = 1; |
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120 | return 0; |
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121 | case 2: |
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122 | oobregion->offset = 6; |
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123 | oobregion->length = 2; |
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124 | return 0; |
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125 | case 3: |
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126 | oobregion->offset = 11; |
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127 | oobregion->length = 2; |
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128 | return 0; |
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129 | default: |
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130 | return -ERANGE; |
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131 | } |
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132 | } |
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133 | |||
134 | static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = { |
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135 | .ecc = rb91x_ooblayout_ecc, |
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136 | .free = rb91x_ooblayout_free, |
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137 | }; |
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138 | #endif /* < 4.6 */ |
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139 | |||
140 | static struct mtd_partition rb91x_nand_partitions[] = { |
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141 | { |
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142 | .name = "booter", |
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143 | .offset = 0, |
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144 | .size = (256 * 1024), |
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145 | .mask_flags = MTD_WRITEABLE, |
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146 | }, { |
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147 | .name = "kernel", |
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148 | .offset = (256 * 1024), |
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149 | .size = (4 * 1024 * 1024) - (256 * 1024), |
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150 | }, { |
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151 | .name = "ubi", |
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152 | .offset = MTDPART_OFS_NXTBLK, |
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153 | .size = MTDPART_SIZ_FULL, |
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154 | }, |
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155 | }; |
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156 | |||
157 | static void rb91x_nand_write(struct rb91x_nand_info *rbni, |
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158 | const u8 *buf, |
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159 | unsigned len) |
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160 | { |
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161 | void __iomem *base = ath79_gpio_base; |
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162 | u32 oe_reg; |
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163 | u32 out_reg; |
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164 | u32 out; |
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165 | unsigned i; |
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166 | |||
167 | /* enable the latch */ |
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168 | gpio_set_value_cansleep(rbni->gpio_nle, 0); |
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169 | |||
170 | oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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171 | out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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172 | |||
173 | /* set data lines to output mode */ |
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174 | __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE), |
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175 | base + AR71XX_GPIO_REG_OE); |
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176 | |||
177 | out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE); |
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178 | for (i = 0; i != len; i++) { |
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179 | u32 data; |
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180 | |||
181 | data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) << |
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182 | RB91X_NAND_HIGH_DATA_SHIFT; |
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183 | data |= buf[i] & RB91X_NAND_LOW_DATA_MASK; |
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184 | data |= out; |
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185 | __raw_writel(data, base + AR71XX_GPIO_REG_OUT); |
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186 | |||
187 | /* deactivate WE line */ |
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188 | data |= RB91X_NAND_NRWE; |
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189 | __raw_writel(data, base + AR71XX_GPIO_REG_OUT); |
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190 | /* flush write */ |
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191 | __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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192 | } |
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193 | |||
194 | /* restore registers */ |
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195 | __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); |
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196 | __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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197 | /* flush write */ |
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198 | __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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199 | |||
200 | /* disable the latch */ |
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201 | gpio_set_value_cansleep(rbni->gpio_nle, 1); |
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202 | } |
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203 | |||
204 | static void rb91x_nand_read(struct rb91x_nand_info *rbni, |
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205 | u8 *read_buf, |
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206 | unsigned len) |
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207 | { |
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208 | void __iomem *base = ath79_gpio_base; |
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209 | u32 oe_reg; |
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210 | u32 out_reg; |
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211 | unsigned i; |
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212 | |||
213 | /* enable read mode */ |
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214 | gpio_set_value_cansleep(rbni->gpio_read, 1); |
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215 | |||
216 | /* enable latch */ |
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217 | gpio_set_value_cansleep(rbni->gpio_nle, 0); |
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218 | |||
219 | /* save registers */ |
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220 | oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE); |
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221 | out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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222 | |||
223 | /* set data lines to input mode */ |
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224 | __raw_writel(oe_reg | RB91X_NAND_DATA_BITS, |
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225 | base + AR71XX_GPIO_REG_OE); |
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226 | |||
227 | for (i = 0; i < len; i++) { |
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228 | u32 in; |
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229 | u8 data; |
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230 | |||
231 | /* activate RE line */ |
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232 | __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR); |
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233 | /* flush write */ |
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234 | __raw_readl(base + AR71XX_GPIO_REG_CLEAR); |
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235 | |||
236 | /* read input lines */ |
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237 | in = __raw_readl(base + AR71XX_GPIO_REG_IN); |
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238 | |||
239 | /* deactivate RE line */ |
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240 | __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET); |
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241 | |||
242 | data = (in & RB91X_NAND_LOW_DATA_MASK); |
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243 | data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) & |
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244 | RB91X_NAND_HIGH_DATA_MASK; |
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245 | |||
246 | read_buf[i] = data; |
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247 | } |
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248 | |||
249 | /* restore registers */ |
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250 | __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT); |
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251 | __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE); |
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252 | /* flush write */ |
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253 | __raw_readl(base + AR71XX_GPIO_REG_OUT); |
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254 | |||
255 | /* disable latch */ |
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256 | gpio_set_value_cansleep(rbni->gpio_nle, 1); |
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257 | |||
258 | /* disable read mode */ |
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259 | gpio_set_value_cansleep(rbni->gpio_read, 0); |
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260 | } |
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261 | |||
262 | static int rb91x_nand_dev_ready(struct mtd_info *mtd) |
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263 | { |
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264 | struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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265 | |||
266 | return gpio_get_value_cansleep(rbni->gpio_rdy); |
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267 | } |
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268 | |||
269 | static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, |
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270 | unsigned int ctrl) |
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271 | { |
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272 | struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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273 | |||
274 | if (ctrl & NAND_CTRL_CHANGE) { |
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275 | gpio_set_value_cansleep(rbni->gpio_cle, |
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276 | (ctrl & NAND_CLE) ? 1 : 0); |
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277 | gpio_set_value_cansleep(rbni->gpio_ale, |
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278 | (ctrl & NAND_ALE) ? 1 : 0); |
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279 | gpio_set_value_cansleep(rbni->gpio_nce, |
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280 | (ctrl & NAND_NCE) ? 0 : 1); |
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281 | } |
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282 | |||
283 | if (cmd != NAND_CMD_NONE) { |
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284 | u8 t = cmd; |
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285 | |||
286 | rb91x_nand_write(rbni, &t, 1); |
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287 | } |
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288 | } |
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289 | |||
290 | static u8 rb91x_nand_read_byte(struct mtd_info *mtd) |
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291 | { |
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292 | struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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293 | u8 data = 0xff; |
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294 | |||
295 | rb91x_nand_read(rbni, &data, 1); |
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296 | |||
297 | return data; |
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298 | } |
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299 | |||
300 | static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) |
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301 | { |
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302 | struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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303 | |||
304 | rb91x_nand_read(rbni, buf, len); |
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305 | } |
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306 | |||
307 | static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) |
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308 | { |
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309 | struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd); |
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310 | |||
311 | rb91x_nand_write(rbni, buf, len); |
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312 | } |
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313 | |||
314 | static int rb91x_nand_gpio_init(struct rb91x_nand_info *info) |
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315 | { |
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316 | int ret; |
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317 | |||
318 | /* |
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319 | * Ensure that the LATCH is disabled before initializing |
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320 | * control lines. |
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321 | */ |
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322 | ret = devm_gpio_request_one(info->dev, info->gpio_nle, |
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323 | GPIOF_OUT_INIT_HIGH, "LATCH enable"); |
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324 | if (ret) |
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325 | return ret; |
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326 | |||
327 | ret = devm_gpio_request_one(info->dev, info->gpio_nce, |
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328 | GPIOF_OUT_INIT_HIGH, "NAND nCE"); |
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329 | if (ret) |
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330 | return ret; |
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331 | |||
332 | ret = devm_gpio_request_one(info->dev, info->gpio_nrw, |
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333 | GPIOF_OUT_INIT_HIGH, "NAND nRW"); |
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334 | if (ret) |
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335 | return ret; |
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336 | |||
337 | ret = devm_gpio_request_one(info->dev, info->gpio_cle, |
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338 | GPIOF_OUT_INIT_LOW, "NAND CLE"); |
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339 | if (ret) |
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340 | return ret; |
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341 | |||
342 | ret = devm_gpio_request_one(info->dev, info->gpio_ale, |
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343 | GPIOF_OUT_INIT_LOW, "NAND ALE"); |
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344 | if (ret) |
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345 | return ret; |
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346 | |||
347 | ret = devm_gpio_request_one(info->dev, info->gpio_read, |
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348 | GPIOF_OUT_INIT_LOW, "NAND READ"); |
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349 | if (ret) |
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350 | return ret; |
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351 | |||
352 | ret = devm_gpio_request_one(info->dev, info->gpio_rdy, |
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353 | GPIOF_IN, "NAND RDY"); |
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354 | return ret; |
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355 | } |
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356 | |||
357 | static int rb91x_nand_probe(struct platform_device *pdev) |
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358 | { |
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359 | struct rb91x_nand_info *rbni; |
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360 | struct rb91x_nand_platform_data *pdata; |
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361 | struct mtd_info *mtd; |
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362 | int ret; |
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363 | |||
364 | pr_info(DRV_DESC "\n"); |
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365 | |||
366 | pdata = dev_get_platdata(&pdev->dev); |
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367 | if (!pdata) |
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368 | return -EINVAL; |
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369 | |||
370 | rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL); |
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371 | if (!rbni) |
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372 | return -ENOMEM; |
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373 | |||
374 | rbni->dev = &pdev->dev; |
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375 | rbni->gpio_nce = pdata->gpio_nce; |
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376 | rbni->gpio_ale = pdata->gpio_ale; |
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377 | rbni->gpio_cle = pdata->gpio_cle; |
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378 | rbni->gpio_read = pdata->gpio_read; |
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379 | rbni->gpio_nrw = pdata->gpio_nrw; |
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380 | rbni->gpio_rdy = pdata->gpio_rdy; |
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381 | rbni->gpio_nle = pdata->gpio_nle; |
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382 | |||
383 | rbni->chip.priv = &rbni; |
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384 | mtd = rbinfo_to_mtd(rbni); |
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385 | |||
386 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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387 | mtd->priv = &rbni->chip; |
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388 | #endif |
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389 | mtd->owner = THIS_MODULE; |
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390 | |||
391 | rbni->chip.cmd_ctrl = rb91x_nand_cmd_ctrl; |
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392 | rbni->chip.dev_ready = rb91x_nand_dev_ready; |
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393 | rbni->chip.read_byte = rb91x_nand_read_byte; |
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394 | rbni->chip.write_buf = rb91x_nand_write_buf; |
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395 | rbni->chip.read_buf = rb91x_nand_read_buf; |
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396 | |||
397 | rbni->chip.chip_delay = 25; |
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398 | rbni->chip.ecc.mode = NAND_ECC_SOFT; |
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399 | #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0) |
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400 | rbni->chip.ecc.algo = NAND_ECC_HAMMING; |
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401 | #endif |
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402 | rbni->chip.options = NAND_NO_SUBPAGE_WRITE; |
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403 | |||
404 | platform_set_drvdata(pdev, rbni); |
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405 | |||
406 | ret = rb91x_nand_gpio_init(rbni); |
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407 | if (ret) |
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408 | return ret; |
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409 | |||
410 | ret = nand_scan_ident(mtd, 1, NULL); |
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411 | if (ret) |
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412 | return ret; |
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413 | |||
414 | if (mtd->writesize == 512) |
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415 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) |
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416 | rbni->chip.ecc.layout = &rb91x_nand_ecclayout; |
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417 | #else |
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418 | mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops); |
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419 | #endif |
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420 | |||
421 | ret = nand_scan_tail(mtd); |
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422 | if (ret) |
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423 | return ret; |
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424 | |||
425 | ret = mtd_device_register(mtd, rb91x_nand_partitions, |
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426 | ARRAY_SIZE(rb91x_nand_partitions)); |
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427 | if (ret) |
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428 | goto err_release_nand; |
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429 | |||
430 | return 0; |
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431 | |||
432 | err_release_nand: |
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433 | nand_release(mtd); |
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434 | return ret; |
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435 | } |
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436 | |||
437 | static int rb91x_nand_remove(struct platform_device *pdev) |
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438 | { |
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439 | struct rb91x_nand_info *info = platform_get_drvdata(pdev); |
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440 | |||
441 | nand_release(rbinfo_to_mtd(info)); |
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442 | |||
443 | return 0; |
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444 | } |
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445 | |||
446 | static struct platform_driver rb91x_nand_driver = { |
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447 | .probe = rb91x_nand_probe, |
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448 | .remove = rb91x_nand_remove, |
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449 | .driver = { |
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450 | .name = RB91X_NAND_DRIVER_NAME, |
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451 | .owner = THIS_MODULE, |
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452 | }, |
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453 | }; |
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454 | |||
455 | module_platform_driver(rb91x_nand_driver); |
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456 | |||
457 | MODULE_DESCRIPTION(DRV_DESC); |
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458 | MODULE_VERSION(DRV_VERSION); |
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459 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
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460 | MODULE_LICENSE("GPL v2"); |