OpenWrt – Blame information for rev 3
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1 | office | 1 | /* |
2 | * TP-LINK TL-WR1043ND v2 board support |
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3 | * |
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4 | * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * Based on the Qualcomm Atheros AP135/AP136 reference board support code |
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7 | * Copyright (c) 2012 Qualcomm Atheros |
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8 | * |
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9 | * Permission to use, copy, modify, and/or distribute this software for any |
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10 | * purpose with or without fee is hereby granted, provided that the above |
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11 | * copyright notice and this permission notice appear in all copies. |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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20 | * |
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21 | */ |
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22 | |||
23 | #include <linux/phy.h> |
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24 | #include <linux/gpio.h> |
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25 | #include <linux/platform_device.h> |
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26 | #include <linux/ar8216_platform.h> |
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27 | |||
28 | #include <asm/mach-ath79/ar71xx_regs.h> |
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29 | |||
30 | #include "common.h" |
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31 | #include "dev-eth.h" |
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32 | #include "dev-gpio-buttons.h" |
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33 | #include "dev-leds-gpio.h" |
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34 | #include "dev-m25p80.h" |
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35 | #include "dev-spi.h" |
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36 | #include "dev-usb.h" |
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37 | #include "dev-wmac.h" |
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38 | #include "machtypes.h" |
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39 | |||
40 | #define TL_WR1043_V2_GPIO_LED_WLAN 12 |
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41 | #define TL_WR1043_V2_GPIO_LED_USB 15 |
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42 | #define TL_WR1043_V2_GPIO_LED_WPS 18 |
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43 | #define TL_WR1043_V2_GPIO_LED_SYSTEM 19 |
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44 | |||
45 | #define TL_WR1043_V2_GPIO_BTN_RESET 16 |
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46 | #define TL_WR1043_V2_GPIO_BTN_RFKILL 17 |
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47 | |||
48 | #define TL_WR1043_V2_GPIO_USB_POWER 21 |
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49 | |||
50 | #define TL_WR1043_V2_KEYS_POLL_INTERVAL 20 /* msecs */ |
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51 | #define TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043_V2_KEYS_POLL_INTERVAL) |
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52 | |||
53 | #define TL_WR1043_V2_WMAC_CALDATA_OFFSET 0x1000 |
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54 | |||
55 | static const char *wr1043nd_v2_part_probes[] = { |
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56 | "tp-link", |
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57 | NULL, |
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58 | }; |
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59 | |||
60 | static struct flash_platform_data wr1043nd_v2_flash_data = { |
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61 | .part_probes = wr1043nd_v2_part_probes, |
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62 | }; |
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63 | |||
64 | static struct gpio_led tl_wr1043_v2_leds_gpio[] __initdata = { |
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65 | { |
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66 | .name = "tp-link:green:wps", |
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67 | .gpio = TL_WR1043_V2_GPIO_LED_WPS, |
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68 | .active_low = 1, |
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69 | }, |
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70 | { |
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71 | .name = "tp-link:green:system", |
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72 | .gpio = TL_WR1043_V2_GPIO_LED_SYSTEM, |
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73 | .active_low = 1, |
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74 | }, |
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75 | { |
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76 | .name = "tp-link:green:wlan", |
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77 | .gpio = TL_WR1043_V2_GPIO_LED_WLAN, |
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78 | .active_low = 1, |
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79 | }, |
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80 | { |
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81 | .name = "tp-link:green:usb", |
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82 | .gpio = TL_WR1043_V2_GPIO_LED_USB, |
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83 | .active_low = 1, |
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84 | }, |
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85 | }; |
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86 | |||
87 | static struct gpio_keys_button tl_wr1043_v2_gpio_keys[] __initdata = { |
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88 | { |
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89 | .desc = "Reset button", |
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90 | .type = EV_KEY, |
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91 | .code = KEY_RESTART, |
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92 | .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, |
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93 | .gpio = TL_WR1043_V2_GPIO_BTN_RESET, |
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94 | .active_low = 1, |
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95 | }, |
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96 | { |
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97 | .desc = "RFKILL button", |
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98 | .type = EV_KEY, |
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99 | .code = KEY_RFKILL, |
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100 | .debounce_interval = TL_WR1043_V2_KEYS_DEBOUNCE_INTERVAL, |
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101 | .gpio = TL_WR1043_V2_GPIO_BTN_RFKILL, |
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102 | .active_low = 1, |
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103 | }, |
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104 | }; |
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105 | |||
106 | static const struct ar8327_led_info tl_wr1043_leds_ar8327[] = { |
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107 | AR8327_LED_INFO(PHY0_0, HW, "tp-link:green:lan4"), |
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108 | AR8327_LED_INFO(PHY1_0, HW, "tp-link:green:lan3"), |
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109 | AR8327_LED_INFO(PHY2_0, HW, "tp-link:green:lan2"), |
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110 | AR8327_LED_INFO(PHY3_0, HW, "tp-link:green:lan1"), |
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111 | AR8327_LED_INFO(PHY4_0, HW, "tp-link:green:wan"), |
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112 | }; |
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113 | |||
114 | /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ |
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115 | static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad0_cfg = { |
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116 | .mode = AR8327_PAD_MAC_SGMII, |
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117 | .sgmii_delay_en = true, |
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118 | }; |
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119 | |||
120 | /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ |
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121 | static struct ar8327_pad_cfg wr1043nd_v2_ar8327_pad6_cfg = { |
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122 | .mode = AR8327_PAD_MAC_RGMII, |
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123 | .txclk_delay_en = true, |
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124 | .rxclk_delay_en = true, |
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125 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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126 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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127 | }; |
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128 | |||
129 | static struct ar8327_led_cfg wr1043nd_v2_ar8327_led_cfg = { |
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130 | .led_ctrl0 = 0xcc35cc35, |
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131 | .led_ctrl1 = 0xca35ca35, |
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132 | .led_ctrl2 = 0xc935c935, |
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133 | .led_ctrl3 = 0x03ffff00, |
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134 | .open_drain = true, |
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135 | }; |
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136 | |||
137 | static struct ar8327_platform_data wr1043nd_v2_ar8327_data = { |
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138 | .pad0_cfg = &wr1043nd_v2_ar8327_pad0_cfg, |
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139 | .pad6_cfg = &wr1043nd_v2_ar8327_pad6_cfg, |
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140 | .port0_cfg = { |
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141 | .force_link = 1, |
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142 | .speed = AR8327_PORT_SPEED_1000, |
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143 | .duplex = 1, |
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144 | .txpause = 1, |
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145 | .rxpause = 1, |
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146 | }, |
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147 | .port6_cfg = { |
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148 | .force_link = 1, |
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149 | .speed = AR8327_PORT_SPEED_1000, |
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150 | .duplex = 1, |
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151 | .txpause = 1, |
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152 | .rxpause = 1, |
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153 | }, |
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154 | .led_cfg = &wr1043nd_v2_ar8327_led_cfg, |
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155 | .num_leds = ARRAY_SIZE(tl_wr1043_leds_ar8327), |
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156 | .leds = tl_wr1043_leds_ar8327, |
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157 | }; |
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158 | |||
159 | static struct mdio_board_info wr1043nd_v2_mdio0_info[] = { |
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160 | { |
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161 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 162 | .phy_addr = 0, |
1 | office | 163 | .platform_data = &wr1043nd_v2_ar8327_data, |
164 | }, |
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165 | }; |
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166 | |||
167 | static void __init tl_wr1043nd_v2_setup(void) |
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168 | { |
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169 | u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); |
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170 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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171 | |||
172 | ath79_register_m25p80(&wr1043nd_v2_flash_data); |
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173 | |||
174 | ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio), |
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175 | tl_wr1043_v2_leds_gpio); |
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176 | ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL, |
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177 | ARRAY_SIZE(tl_wr1043_v2_gpio_keys), |
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178 | tl_wr1043_v2_gpio_keys); |
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179 | |||
180 | ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac); |
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181 | |||
182 | mdiobus_register_board_info(wr1043nd_v2_mdio0_info, |
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183 | ARRAY_SIZE(wr1043nd_v2_mdio0_info)); |
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184 | ath79_register_mdio(0, 0x0); |
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185 | |||
186 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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187 | |||
188 | /* GMAC0 is connected to the RMGII interface */ |
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189 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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190 | ath79_eth0_data.phy_mask = BIT(0); |
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191 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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192 | ath79_eth0_pll_data.pll_1000 = 0x56000000; |
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193 | |||
194 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
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195 | ath79_register_eth(0); |
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196 | |||
197 | /* GMAC1 is connected to the SGMII interface */ |
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198 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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199 | ath79_eth1_data.speed = SPEED_1000; |
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200 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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201 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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202 | |||
203 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); |
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204 | ath79_register_eth(1); |
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205 | |||
206 | ath79_register_usb(); |
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207 | |||
208 | gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER, |
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209 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
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210 | "USB power"); |
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211 | } |
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212 | |||
213 | MIPS_MACHINE(ATH79_MACH_TL_WR1043ND_V2, "TL-WR1043ND-v2", |
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214 | "TP-LINK TL-WR1043ND v2", tl_wr1043nd_v2_setup); |
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215 |