OpenWrt – Blame information for rev 2
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * TP-LINK TL-WDR3320 v2 board support |
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3 | * |
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4 | * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2015 Weijie Gao <hackpascal@gmail.com> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #include <linux/pci.h> |
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13 | #include <linux/phy.h> |
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14 | #include <linux/gpio.h> |
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15 | #include <linux/platform_device.h> |
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16 | #include <linux/ath9k_platform.h> |
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17 | |||
18 | #include <asm/mach-ath79/ar71xx_regs.h> |
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19 | |||
20 | #include "common.h" |
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21 | #include "dev-ap9x-pci.h" |
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22 | #include "dev-eth.h" |
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23 | #include "dev-gpio-buttons.h" |
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24 | #include "dev-leds-gpio.h" |
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25 | #include "dev-m25p80.h" |
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26 | #include "dev-spi.h" |
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27 | #include "dev-usb.h" |
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28 | #include "dev-wmac.h" |
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29 | #include "machtypes.h" |
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30 | |||
31 | #define WDR3320_GPIO_LED_WLAN5G 12 |
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32 | #define WDR3320_GPIO_LED_SYSTEM 14 |
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33 | #define WDR3320_GPIO_LED_QSS 15 |
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34 | #define WDR3320_GPIO_LED_WAN 4 |
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35 | #define WDR3320_GPIO_LED_LAN1 18 |
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36 | #define WDR3320_GPIO_LED_LAN2 20 |
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37 | #define WDR3320_GPIO_LED_LAN3 21 |
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38 | #define WDR3320_GPIO_LED_LAN4 22 |
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39 | |||
40 | #define WDR3320_GPIO_BTN_RESET 16 |
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41 | |||
42 | #define WDR3320_KEYS_POLL_INTERVAL 20 /* msecs */ |
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43 | #define WDR3320_KEYS_DEBOUNCE_INTERVAL (3 * WDR3320_KEYS_POLL_INTERVAL) |
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44 | |||
45 | #define WDR3320_WMAC_CALDATA_OFFSET 0x1000 |
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46 | #define WDR3320_PCIE_CALDATA_OFFSET 0x5000 |
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47 | |||
48 | static const char *wdr3320_part_probes[] = { |
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49 | "tp-link", |
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50 | NULL, |
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51 | }; |
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52 | |||
53 | static struct flash_platform_data wdr3320_flash_data = { |
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54 | .part_probes = wdr3320_part_probes, |
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55 | }; |
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56 | |||
57 | static struct gpio_led wdr3320_leds_gpio[] __initdata = { |
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58 | { |
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59 | .name = "tp-link:green:qss", |
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60 | .gpio = WDR3320_GPIO_LED_QSS, |
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61 | .active_low = 1, |
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62 | }, |
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63 | { |
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64 | .name = "tp-link:green:system", |
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65 | .gpio = WDR3320_GPIO_LED_SYSTEM, |
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66 | .active_low = 1, |
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67 | }, |
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68 | { |
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69 | .name = "tp-link:green:wlan5g", |
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70 | .gpio = WDR3320_GPIO_LED_WLAN5G, |
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71 | .active_low = 1, |
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72 | }, |
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73 | }; |
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74 | |||
75 | static struct gpio_keys_button wdr3320_gpio_keys[] __initdata = { |
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76 | { |
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77 | .desc = "reset", |
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78 | .type = EV_KEY, |
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79 | .code = KEY_RESTART, |
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80 | .debounce_interval = WDR3320_KEYS_DEBOUNCE_INTERVAL, |
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81 | .gpio = WDR3320_GPIO_BTN_RESET, |
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82 | .active_low = 1, |
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83 | }, |
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84 | }; |
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85 | |||
86 | static void __init wdr3320_setup(void) |
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87 | { |
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88 | u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); |
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89 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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90 | u8 tmpmac[ETH_ALEN]; |
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91 | |||
92 | ath79_register_m25p80(&wdr3320_flash_data); |
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93 | ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr3320_leds_gpio), |
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94 | wdr3320_leds_gpio); |
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95 | ath79_register_gpio_keys_polled(-1, WDR3320_KEYS_POLL_INTERVAL, |
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96 | ARRAY_SIZE(wdr3320_gpio_keys), |
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97 | wdr3320_gpio_keys); |
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98 | |||
99 | ath79_init_mac(tmpmac, mac, 0); |
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100 | ath79_register_wmac(art + WDR3320_WMAC_CALDATA_OFFSET, tmpmac); |
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101 | |||
102 | ath79_init_mac(tmpmac, mac, -1); |
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103 | ap9x_pci_setup_wmac_led_pin(0, 0); |
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104 | ap91_pci_init(art + WDR3320_PCIE_CALDATA_OFFSET, tmpmac); |
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105 | |||
106 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); |
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107 | |||
108 | ath79_register_mdio(1, 0x0); |
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109 | |||
110 | /* LAN */ |
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111 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); |
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112 | |||
113 | /* GMAC1 is connected to the internal switch */ |
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114 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
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115 | |||
116 | ath79_register_eth(1); |
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117 | |||
118 | /* WAN */ |
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119 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
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120 | |||
121 | /* GMAC0 is connected to the PHY4 of the internal switch */ |
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122 | ath79_switch_data.phy4_mii_en = 1; |
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123 | ath79_switch_data.phy_poll_mask = BIT(4); |
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124 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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125 | ath79_eth0_data.phy_mask = BIT(4); |
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126 | ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; |
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127 | |||
128 | ath79_register_eth(0); |
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129 | |||
130 | ath79_register_usb(); |
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131 | |||
132 | ath79_gpio_output_select(WDR3320_GPIO_LED_LAN1, |
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133 | AR934X_GPIO_OUT_LED_LINK0); |
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134 | ath79_gpio_output_select(WDR3320_GPIO_LED_LAN2, |
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135 | AR934X_GPIO_OUT_LED_LINK1); |
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136 | ath79_gpio_output_select(WDR3320_GPIO_LED_LAN3, |
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137 | AR934X_GPIO_OUT_LED_LINK2); |
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138 | ath79_gpio_output_select(WDR3320_GPIO_LED_LAN4, |
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139 | AR934X_GPIO_OUT_LED_LINK3); |
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140 | ath79_gpio_output_select(WDR3320_GPIO_LED_WAN, |
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141 | AR934X_GPIO_OUT_LED_LINK4); |
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142 | } |
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143 | |||
144 | MIPS_MACHINE(ATH79_MACH_TL_WDR3320_V2, "TL-WDR3320-v2", |
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145 | "TP-LINK TL-WDR3320 v2", |
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146 | wdr3320_setup); |