OpenWrt – Blame information for rev 3
?pathlinks?
Rev | Author | Line No. | Line |
---|---|---|---|
1 | office | 1 | /* |
2 | * MikroTik SPI-NOR RouterBOARDs support |
||
3 | * |
||
4 | * - MikroTik RouterBOARD mAP 2nD |
||
5 | * - MikroTik RouterBOARD mAP L-2nD |
||
6 | * - MikroTik RouterBOARD 911-2Hn (911 Lite2) |
||
7 | * - MikroTik RouterBOARD 911-5Hn (911 Lite5) |
||
8 | * - MikroTik RouterBOARD 941L-2nD |
||
9 | * - MikroTik RouterBOARD 951Ui-2nD |
||
10 | * - MikroTik RouterBOARD 952Ui-5ac2nD |
||
11 | * - MikroTik RouterBOARD 962UiGS-5HacT2HnT |
||
12 | * - MikroTik RouterBOARD 750UP r2 |
||
13 | * - MikroTik RouterBOARD 750P-PBr2 |
||
14 | * - MikroTik RouterBOARD 750 r2 |
||
15 | * - MikroTik RouterBOARD LHG 5nD |
||
16 | * - MikroTik RouterBOARD wAP2nD |
||
17 | * - MikroTik RouterBOARD wAP G-5HacT2HnDwAP (wAP AC) |
||
18 | * |
||
19 | * Preliminary support for the following hardware |
||
20 | * - MikroTik RouterBOARD cAP2nD |
||
21 | * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same |
||
22 | * hardware as the mAP L-2nD. It is unknown if they share the same board |
||
23 | * identifier. |
||
24 | * |
||
3 | office | 25 | * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org> |
1 | office | 26 | * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net> |
27 | * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au> |
||
28 | * |
||
29 | * This program is free software; you can redistribute it and/or modify it |
||
30 | * under the terms of the GNU General Public License version 2 as published |
||
31 | * by the Free Software Foundation. |
||
32 | */ |
||
33 | |||
34 | #include <linux/pci.h> |
||
35 | #include <linux/platform_device.h> |
||
36 | #include <linux/phy.h> |
||
37 | #include <linux/routerboot.h> |
||
38 | #include <linux/gpio.h> |
||
39 | |||
40 | #include <linux/spi/spi.h> |
||
41 | #include <linux/spi/74x164.h> |
||
42 | |||
43 | #include <linux/mtd/mtd.h> |
||
44 | #include <linux/mtd/partitions.h> |
||
45 | |||
46 | #include <linux/ar8216_platform.h> |
||
47 | #include <linux/platform_data/phy-at803x.h> |
||
48 | #include <linux/platform_data/mdio-gpio.h> |
||
49 | |||
50 | #include <asm/prom.h> |
||
51 | #include <asm/mach-ath79/ar71xx_regs.h> |
||
52 | #include <asm/mach-ath79/ath79.h> |
||
53 | |||
54 | #include "common.h" |
||
55 | #include "dev-eth.h" |
||
56 | #include "dev-spi.h" |
||
57 | #include "dev-gpio-buttons.h" |
||
58 | #include "dev-leds-gpio.h" |
||
59 | #include "dev-m25p80.h" |
||
60 | #include "dev-usb.h" |
||
61 | #include "dev-wmac.h" |
||
62 | #include "machtypes.h" |
||
63 | #include "pci.h" |
||
64 | #include "routerboot.h" |
||
65 | |||
66 | #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */ |
||
67 | #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL) |
||
68 | |||
69 | #define RBSPI_HAS_USB BIT(0) |
||
70 | #define RBSPI_HAS_WLAN0 BIT(1) |
||
71 | #define RBSPI_HAS_WLAN1 BIT(2) |
||
72 | #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */ |
||
73 | #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */ |
||
74 | #define RBSPI_HAS_POE BIT(5) |
||
75 | #define RBSPI_HAS_MDIO1 BIT(6) |
||
76 | #define RBSPI_HAS_PCI BIT(7) |
||
77 | |||
78 | #define RB_ROUTERBOOT_OFFSET 0x0000 |
||
79 | #define RB_BIOS_SIZE 0x1000 |
||
80 | #define RB_SOFT_CFG_SIZE 0x1000 |
||
81 | |||
82 | /* Flash partitions indexes */ |
||
83 | enum { |
||
84 | RBSPI_PART_RBOOT, |
||
85 | RBSPI_PART_HCONF, |
||
86 | RBSPI_PART_BIOS, |
||
87 | RBSPI_PART_RBOOT2, |
||
88 | RBSPI_PART_SCONF, |
||
89 | RBSPI_PART_FIRMW, |
||
90 | RBSPI_PARTS |
||
91 | }; |
||
92 | |||
93 | static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS]; |
||
94 | |||
95 | /* |
||
96 | * Setup the SPI flash partition table based on initial parsing. |
||
97 | * The kernel can be at any aligned position and have any size. |
||
98 | */ |
||
99 | static void __init rbspi_init_partitions(const struct rb_info *info) |
||
100 | { |
||
101 | struct mtd_partition *parts = rbspi_spi_partitions; |
||
102 | memset(parts, 0x0, sizeof(*parts)); |
||
103 | |||
104 | parts[RBSPI_PART_RBOOT].name = "routerboot"; |
||
105 | parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET; |
||
106 | parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs; |
||
107 | parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE; |
||
108 | |||
109 | parts[RBSPI_PART_HCONF].name = "hard_config"; |
||
110 | parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs; |
||
111 | parts[RBSPI_PART_HCONF].size = info->hard_cfg_size; |
||
112 | parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE; |
||
113 | |||
114 | parts[RBSPI_PART_BIOS].name = "bios"; |
||
115 | parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs |
||
116 | + info->hard_cfg_size; |
||
117 | parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE; |
||
118 | parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE; |
||
119 | |||
120 | parts[RBSPI_PART_RBOOT2].name = "routerboot2"; |
||
121 | parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset |
||
122 | + RB_BIOS_SIZE; |
||
123 | parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs |
||
124 | - parts[RBSPI_PART_RBOOT2].offset; |
||
125 | parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE; |
||
126 | |||
127 | parts[RBSPI_PART_SCONF].name = "soft_config"; |
||
128 | parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs; |
||
129 | parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE; |
||
130 | |||
131 | parts[RBSPI_PART_FIRMW].name = "firmware"; |
||
132 | parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset |
||
133 | + parts[RBSPI_PART_SCONF].size; |
||
134 | parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL; |
||
135 | } |
||
136 | |||
137 | static struct flash_platform_data rbspi_spi_flash_data = { |
||
138 | .parts = rbspi_spi_partitions, |
||
139 | .nr_parts = ARRAY_SIZE(rbspi_spi_partitions), |
||
140 | }; |
||
141 | |||
142 | /* |
||
143 | * Several boards only have a single reset button, use a common |
||
144 | * structure for that. |
||
145 | */ |
||
146 | static struct gpio_keys_button rbspi_gpio_keys_reset[] __initdata = { |
||
147 | { |
||
148 | .desc = "Reset button", |
||
149 | .type = EV_KEY, |
||
150 | .code = KEY_RESTART, |
||
151 | .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL, |
||
152 | .gpio = -ENOENT, /* filled dynamically */ |
||
153 | .active_low = 1, |
||
154 | }, |
||
155 | }; |
||
156 | |||
157 | /* RB mAP L-2nD gpios */ |
||
158 | #define RBMAPL_GPIO_LED_POWER 17 |
||
159 | #define RBMAPL_GPIO_LED_USER 14 |
||
160 | #define RBMAPL_GPIO_LED_ETH 4 |
||
161 | #define RBMAPL_GPIO_LED_WLAN 11 |
||
162 | #define RBMAPL_GPIO_BTN_RESET 16 |
||
163 | |||
164 | static struct gpio_led rbmapl_leds[] __initdata = { |
||
165 | { |
||
166 | .name = "rb:green:power", |
||
167 | .gpio = RBMAPL_GPIO_LED_POWER, |
||
168 | .active_low = 0, |
||
169 | .default_state = LEDS_GPIO_DEFSTATE_ON, |
||
170 | }, { |
||
171 | .name = "rb:green:user", |
||
172 | .gpio = RBMAPL_GPIO_LED_USER, |
||
173 | .active_low = 0, |
||
174 | }, { |
||
175 | .name = "rb:green:eth", |
||
176 | .gpio = RBMAPL_GPIO_LED_ETH, |
||
177 | .active_low = 0, |
||
178 | }, { |
||
179 | .name = "rb:green:wlan", |
||
180 | .gpio = RBMAPL_GPIO_LED_WLAN, |
||
181 | .active_low = 0, |
||
182 | }, |
||
183 | }; |
||
184 | |||
185 | /* RB 941L-2nD gpios */ |
||
186 | #define RBHAPL_GPIO_LED_USER 14 |
||
187 | #define RBHAPL_GPIO_BTN_RESET 16 |
||
188 | |||
189 | static struct gpio_led rbhapl_leds[] __initdata = { |
||
190 | { |
||
191 | .name = "rb:green:user", |
||
192 | .gpio = RBHAPL_GPIO_LED_USER, |
||
193 | .active_low = 1, |
||
194 | }, |
||
195 | }; |
||
196 | |||
197 | /* common RB SSRs */ |
||
198 | #define RBSPI_SSR_GPIO_BASE 40 |
||
199 | #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit)) |
||
200 | |||
201 | /* RB 951Ui-2nD gpios */ |
||
202 | #define RB952_SSR_BIT_LED_LAN1 0 |
||
203 | #define RB952_SSR_BIT_LED_LAN2 1 |
||
204 | #define RB952_SSR_BIT_LED_LAN3 2 |
||
205 | #define RB952_SSR_BIT_LED_LAN4 3 |
||
206 | #define RB952_SSR_BIT_LED_LAN5 4 |
||
207 | #define RB952_SSR_BIT_USB_POWER 5 |
||
208 | #define RB952_SSR_BIT_LED_WLAN 6 |
||
209 | #define RB952_GPIO_SSR_CS 11 |
||
210 | #define RB952_GPIO_LED_USER 4 |
||
211 | #define RB952_GPIO_POE_POWER 14 |
||
212 | #define RB952_GPIO_POE_STATUS 12 |
||
213 | #define RB952_GPIO_BTN_RESET 16 |
||
3 | office | 214 | #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER) |
1 | office | 215 | #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1) |
216 | #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2) |
||
217 | #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3) |
||
218 | #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4) |
||
219 | #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5) |
||
220 | #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN) |
||
221 | |||
222 | static struct gpio_led rb952_leds[] __initdata = { |
||
223 | { |
||
224 | .name = "rb:green:user", |
||
225 | .gpio = RB952_GPIO_LED_USER, |
||
226 | .active_low = 0, |
||
227 | }, { |
||
228 | .name = "rb:blue:wlan", |
||
229 | .gpio = RB952_GPIO_LED_WLAN, |
||
230 | .active_low = 1, |
||
231 | }, { |
||
232 | .name = "rb:green:port1", |
||
233 | .gpio = RB952_GPIO_LED_LAN1, |
||
234 | .active_low = 1, |
||
235 | }, { |
||
236 | .name = "rb:green:port2", |
||
237 | .gpio = RB952_GPIO_LED_LAN2, |
||
238 | .active_low = 1, |
||
239 | }, { |
||
240 | .name = "rb:green:port3", |
||
241 | .gpio = RB952_GPIO_LED_LAN3, |
||
242 | .active_low = 1, |
||
243 | }, { |
||
244 | .name = "rb:green:port4", |
||
245 | .gpio = RB952_GPIO_LED_LAN4, |
||
246 | .active_low = 1, |
||
247 | }, { |
||
248 | .name = "rb:green:port5", |
||
249 | .gpio = RB952_GPIO_LED_LAN5, |
||
250 | .active_low = 1, |
||
251 | }, |
||
252 | }; |
||
253 | |||
254 | |||
255 | /* RB 962UiGS-5HacT2HnT gpios */ |
||
256 | #define RB962_GPIO_POE_STATUS 2 |
||
257 | #define RB962_GPIO_POE_POWER 3 |
||
258 | #define RB962_GPIO_LED_USER 12 |
||
3 | office | 259 | #define RB962_GPIO_USB_POWER 13 |
1 | office | 260 | #define RB962_GPIO_BTN_RESET 20 |
261 | |||
262 | static struct gpio_led rb962_leds_gpio[] __initdata = { |
||
263 | { |
||
264 | .name = "rb:green:user", |
||
265 | .gpio = RB962_GPIO_LED_USER, |
||
266 | .active_low = 1, |
||
267 | }, |
||
268 | }; |
||
269 | |||
270 | static const struct ar8327_led_info rb962_leds_ar8327[] = { |
||
271 | AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"), |
||
272 | AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"), |
||
273 | AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"), |
||
274 | AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"), |
||
275 | AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"), |
||
276 | }; |
||
277 | |||
278 | static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = { |
||
279 | .mode = AR8327_PAD_MAC_RGMII, |
||
280 | .txclk_delay_en = true, |
||
281 | .rxclk_delay_en = true, |
||
282 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
||
283 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
||
284 | .mac06_exchange_dis = true, |
||
285 | }; |
||
286 | |||
287 | static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = { |
||
288 | /* Use SGMII interface for GMAC6 of the AR8337 switch */ |
||
289 | .mode = AR8327_PAD_MAC_SGMII, |
||
290 | .rxclk_delay_en = true, |
||
291 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0, |
||
292 | }; |
||
293 | |||
294 | static struct ar8327_led_cfg rb962_ar8327_led_cfg = { |
||
295 | .led_ctrl0 = 0xc737c737, |
||
296 | .led_ctrl1 = 0x00000000, |
||
297 | .led_ctrl2 = 0x00000000, |
||
298 | .led_ctrl3 = 0x0030c300, |
||
299 | .open_drain = false, |
||
300 | }; |
||
301 | |||
302 | static struct ar8327_platform_data rb962_ar8327_data = { |
||
303 | .pad0_cfg = &rb962_ar8327_pad0_cfg, |
||
304 | .pad6_cfg = &rb962_ar8327_pad6_cfg, |
||
305 | .port0_cfg = { |
||
306 | .force_link = 1, |
||
307 | .speed = AR8327_PORT_SPEED_1000, |
||
308 | .duplex = 1, |
||
309 | .txpause = 1, |
||
310 | .rxpause = 1, |
||
311 | }, |
||
312 | .port6_cfg = { |
||
313 | .force_link = 1, |
||
314 | .speed = AR8327_PORT_SPEED_1000, |
||
315 | .duplex = 1, |
||
316 | .txpause = 1, |
||
317 | .rxpause = 1, |
||
318 | }, |
||
319 | .led_cfg = &rb962_ar8327_led_cfg, |
||
320 | .num_leds = ARRAY_SIZE(rb962_leds_ar8327), |
||
321 | .leds = rb962_leds_ar8327, |
||
322 | }; |
||
323 | |||
324 | static struct mdio_board_info rb962_mdio0_info[] = { |
||
325 | { |
||
326 | .bus_id = "ag71xx-mdio.0", |
||
3 | office | 327 | .phy_addr = 0, |
1 | office | 328 | .platform_data = &rb962_ar8327_data, |
329 | }, |
||
330 | }; |
||
331 | |||
332 | /* RB wAP-2nD gpios */ |
||
333 | #define RBWAP_GPIO_LED_USER 14 |
||
334 | #define RBWAP_GPIO_LED_WLAN 11 |
||
335 | #define RBWAP_GPIO_BTN_RESET 16 |
||
336 | |||
337 | static struct gpio_led rbwap_leds[] __initdata = { |
||
338 | { |
||
339 | .name = "rb:green:user", |
||
340 | .gpio = RBWAP_GPIO_LED_USER, |
||
341 | .active_low = 1, |
||
342 | }, { |
||
343 | .name = "rb:green:wlan", |
||
344 | .gpio = RBWAP_GPIO_LED_WLAN, |
||
345 | .active_low = 1, |
||
346 | }, |
||
347 | }; |
||
348 | |||
349 | /* RB cAP-2nD gpios */ |
||
350 | #define RBCAP_GPIO_LED_1 14 |
||
351 | #define RBCAP_GPIO_LED_2 12 |
||
352 | #define RBCAP_GPIO_LED_3 11 |
||
353 | #define RBCAP_GPIO_LED_4 4 |
||
354 | #define RBCAP_GPIO_LED_ALL 13 |
||
355 | |||
356 | static struct gpio_led rbcap_leds[] __initdata = { |
||
357 | { |
||
358 | .name = "rb:green:rssi1", |
||
359 | .gpio = RBCAP_GPIO_LED_1, |
||
360 | .active_low = 1, |
||
361 | }, { |
||
362 | .name = "rb:green:rssi2", |
||
363 | .gpio = RBCAP_GPIO_LED_2, |
||
364 | .active_low = 1, |
||
365 | }, { |
||
366 | .name = "rb:green:rssi3", |
||
367 | .gpio = RBCAP_GPIO_LED_3, |
||
368 | .active_low = 1, |
||
369 | }, { |
||
370 | .name = "rb:green:rssi4", |
||
371 | .gpio = RBCAP_GPIO_LED_4, |
||
372 | .active_low = 1, |
||
373 | }, |
||
374 | }; |
||
375 | |||
376 | /* RB mAP-2nD gpios */ |
||
377 | #define RBMAP_SSR_BIT_LED_LAN1 0 |
||
378 | #define RBMAP_SSR_BIT_LED_LAN2 1 |
||
379 | #define RBMAP_SSR_BIT_LED_POEO 2 |
||
380 | #define RBMAP_SSR_BIT_LED_USER 3 |
||
381 | #define RBMAP_SSR_BIT_LED_WLAN 4 |
||
382 | #define RBMAP_SSR_BIT_USB_POWER 5 |
||
383 | #define RBMAP_SSR_BIT_LED_APCAP 6 |
||
384 | #define RBMAP_GPIO_BTN_RESET 16 |
||
385 | #define RBMAP_GPIO_SSR_CS 11 |
||
386 | #define RBMAP_GPIO_LED_POWER 4 |
||
387 | #define RBMAP_GPIO_POE_POWER 14 |
||
388 | #define RBMAP_GPIO_POE_STATUS 12 |
||
3 | office | 389 | #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER) |
1 | office | 390 | #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1) |
391 | #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2) |
||
392 | #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO) |
||
393 | #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER) |
||
394 | #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN) |
||
395 | #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP) |
||
396 | |||
397 | static struct gpio_led rbmap_leds[] __initdata = { |
||
398 | { |
||
399 | .name = "rb:green:power", |
||
400 | .gpio = RBMAP_GPIO_LED_POWER, |
||
401 | .active_low = 1, |
||
402 | .default_state = LEDS_GPIO_DEFSTATE_ON, |
||
403 | }, { |
||
404 | .name = "rb:green:eth1", |
||
405 | .gpio = RBMAP_GPIO_LED_LAN1, |
||
406 | .active_low = 1, |
||
407 | }, { |
||
408 | .name = "rb:green:eth2", |
||
409 | .gpio = RBMAP_GPIO_LED_LAN2, |
||
410 | .active_low = 1, |
||
411 | }, { |
||
412 | .name = "rb:red:poe_out", |
||
413 | .gpio = RBMAP_GPIO_LED_POEO, |
||
414 | .active_low = 1, |
||
415 | }, { |
||
416 | .name = "rb:green:user", |
||
417 | .gpio = RBMAP_GPIO_LED_USER, |
||
418 | .active_low = 1, |
||
419 | }, { |
||
420 | .name = "rb:green:wlan", |
||
421 | .gpio = RBMAP_GPIO_LED_WLAN, |
||
422 | .active_low = 1, |
||
423 | }, { |
||
424 | .name = "rb:green:ap_cap", |
||
425 | .gpio = RBMAP_GPIO_LED_APCAP, |
||
426 | .active_low = 1, |
||
427 | }, |
||
428 | }; |
||
429 | |||
430 | /* RB LHG 5nD gpios */ |
||
431 | #define RBLHG_GPIO_LED_0 13 |
||
432 | #define RBLHG_GPIO_LED_1 12 |
||
433 | #define RBLHG_GPIO_LED_2 4 |
||
434 | #define RBLHG_GPIO_LED_3 21 |
||
435 | #define RBLHG_GPIO_LED_4 18 |
||
436 | #define RBLHG_GPIO_LED_ETH 14 |
||
437 | #define RBLHG_GPIO_LED_POWER 11 |
||
438 | #define RBLHG_GPIO_LED_USER 20 |
||
439 | #define RBLHG_GPIO_BTN_RESET 15 |
||
440 | |||
441 | static struct gpio_led rblhg_leds[] __initdata = { |
||
442 | { |
||
443 | .name = "rb:green:rssi0", |
||
444 | .gpio = RBLHG_GPIO_LED_0, |
||
445 | .active_low = 1, |
||
446 | }, { |
||
447 | .name = "rb:green:rssi1", |
||
448 | .gpio = RBLHG_GPIO_LED_1, |
||
449 | .active_low = 1, |
||
450 | }, { |
||
451 | .name = "rb:green:rssi2", |
||
452 | .gpio = RBLHG_GPIO_LED_2, |
||
453 | .active_low = 1, |
||
454 | }, { |
||
455 | .name = "rb:green:rssi3", |
||
456 | .gpio = RBLHG_GPIO_LED_3, |
||
457 | .active_low = 1, |
||
458 | }, { |
||
459 | .name = "rb:green:rssi4", |
||
460 | .gpio = RBLHG_GPIO_LED_4, |
||
461 | .active_low = 1, |
||
462 | }, { |
||
463 | .name = "rb:green:eth", |
||
464 | .gpio = RBLHG_GPIO_LED_ETH, |
||
465 | .active_low = 1, |
||
466 | }, { |
||
467 | .name = "rb:green:user", |
||
468 | .gpio = RBLHG_GPIO_LED_USER, |
||
469 | .active_low = 1, |
||
470 | }, { |
||
471 | .name = "rb:blue:power", |
||
472 | .gpio = RBLHG_GPIO_LED_POWER, |
||
473 | .active_low = 0, |
||
474 | .default_state = LEDS_GPIO_DEFSTATE_ON, |
||
475 | }, |
||
476 | }; |
||
477 | |||
478 | /* RB w APG-5HacT2HnD (wAP AC) gpios*/ |
||
479 | #define RBWAPGSC_WIFI_LED_1 1 |
||
480 | #define RBWAPGSC_WIFI_LED_2 8 |
||
481 | #define RBWAPGSC_WIFI_LED_3 9 |
||
482 | #define RBWAPGSC_GPIO_LED_POWER 16 |
||
483 | #define RBWAPGSC_GPIO_BTN_RESET 1 |
||
484 | #define RBWAPGSC_GPIO_MDIO_MDC 12 |
||
485 | #define RBWAPGSC_GPIO_MDIO_DATA 11 |
||
486 | #define RBWAPGSC_MDIO_PHYADDR 0 |
||
487 | |||
488 | static struct gpio_led rbwapgsc_leds[] __initdata = { |
||
489 | { |
||
490 | .name = "rb:green:power", |
||
491 | .gpio = RBWAPGSC_GPIO_LED_POWER, |
||
492 | .active_low = 1, |
||
493 | .default_state = LEDS_GPIO_DEFSTATE_ON, |
||
494 | }, |
||
495 | }; |
||
496 | |||
497 | static struct mdio_gpio_platform_data rbwapgsc_mdio_data = { |
||
498 | .mdc = RBWAPGSC_GPIO_MDIO_MDC, |
||
499 | .mdio = RBWAPGSC_GPIO_MDIO_DATA, |
||
500 | .phy_mask = ~BIT(RBWAPGSC_MDIO_PHYADDR), |
||
501 | }; |
||
502 | |||
503 | static struct platform_device rbwapgsc_phy_device = { |
||
504 | .name = "mdio-gpio", |
||
505 | .id = 1, |
||
506 | .dev = { |
||
507 | .platform_data = &rbwapgsc_mdio_data |
||
508 | }, |
||
509 | }; |
||
510 | |||
511 | /* RB911L GPIOs */ |
||
512 | #define RB911L_GPIO_BTN_RESET 15 |
||
513 | #define RB911L_GPIO_LED_1 13 |
||
514 | #define RB911L_GPIO_LED_2 12 |
||
515 | #define RB911L_GPIO_LED_3 4 |
||
516 | #define RB911L_GPIO_LED_4 21 |
||
517 | #define RB911L_GPIO_LED_5 18 |
||
518 | #define RB911L_GPIO_LED_ETH 20 |
||
519 | #define RB911L_GPIO_LED_POWER 11 |
||
520 | #define RB911L_GPIO_LED_USER 3 |
||
3 | office | 521 | #define RB911L_GPIO_PIN_HOLE 14 /* for reference */ |
1 | office | 522 | |
523 | static struct gpio_led rb911l_leds[] __initdata = { |
||
524 | { |
||
525 | .name = "rb:green:eth", |
||
526 | .gpio = RB911L_GPIO_LED_ETH, |
||
527 | .active_low = 1, |
||
528 | }, { |
||
529 | .name = "rb:green:led1", |
||
530 | .gpio = RB911L_GPIO_LED_1, |
||
531 | .active_low = 1, |
||
532 | }, { |
||
533 | .name = "rb:green:led2", |
||
534 | .gpio = RB911L_GPIO_LED_2, |
||
535 | .active_low = 1, |
||
536 | }, { |
||
537 | .name = "rb:green:led3", |
||
538 | .gpio = RB911L_GPIO_LED_3, |
||
539 | .active_low = 1, |
||
540 | }, { |
||
541 | .name = "rb:green:led4", |
||
542 | .gpio = RB911L_GPIO_LED_4, |
||
543 | .active_low = 1, |
||
544 | }, { |
||
545 | .name = "rb:green:led5", |
||
546 | .gpio = RB911L_GPIO_LED_5, |
||
547 | .active_low = 1, |
||
548 | }, { |
||
549 | .name = "rb:green:power", |
||
550 | .gpio = RB911L_GPIO_LED_POWER, |
||
551 | .default_state = LEDS_GPIO_DEFSTATE_ON, |
||
552 | .open_drain = 1, |
||
553 | }, { |
||
554 | .name = "rb:green:user", |
||
555 | .gpio = RB911L_GPIO_LED_USER, |
||
556 | .active_low = 1, |
||
557 | .open_drain = 1, |
||
558 | }, |
||
559 | }; |
||
560 | |||
561 | static struct gen_74x164_chip_platform_data rbspi_ssr_data = { |
||
562 | .base = RBSPI_SSR_GPIO_BASE, |
||
563 | .num_registers = 1, |
||
564 | }; |
||
565 | |||
566 | /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */ |
||
567 | static int rbspi_spi_cs_gpios[] = { |
||
568 | -ENOENT, /* CS0 is always -ENOENT: natively handled */ |
||
569 | -ENOENT, /* CS1 can be updated by the code as necessary */ |
||
570 | }; |
||
571 | |||
572 | static struct ath79_spi_platform_data rbspi_ath79_spi_data = { |
||
573 | .bus_num = 0, |
||
574 | .cs_gpios = rbspi_spi_cs_gpios, |
||
575 | }; |
||
576 | |||
577 | /* |
||
578 | * Global spi_board_info: devices that don't have an SSR only have the SPI NOR |
||
579 | * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1 |
||
580 | */ |
||
581 | static struct spi_board_info rbspi_spi_info[] = { |
||
582 | { |
||
583 | .bus_num = 0, |
||
584 | .chip_select = 0, |
||
585 | .max_speed_hz = 25000000, |
||
586 | .modalias = "m25p80", |
||
587 | .platform_data = &rbspi_spi_flash_data, |
||
588 | }, { |
||
589 | .bus_num = 0, |
||
590 | .chip_select = 1, |
||
591 | .max_speed_hz = 25000000, |
||
592 | .modalias = "74x164", |
||
593 | .platform_data = &rbspi_ssr_data, |
||
594 | } |
||
595 | }; |
||
596 | |||
597 | void __init rbspi_wlan_init(u16 id, int wmac_offset) |
||
598 | { |
||
599 | char *art_buf; |
||
600 | u8 wlan_mac[ETH_ALEN]; |
||
601 | |||
602 | art_buf = rb_get_ext_wlan_data(id); |
||
603 | if (!art_buf) |
||
604 | return; |
||
605 | |||
606 | ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset); |
||
607 | ath79_register_wmac(art_buf + 0x1000, wlan_mac); |
||
608 | |||
609 | kfree(art_buf); |
||
610 | } |
||
611 | |||
612 | #define RBSPI_MACH_BUFLEN 64 |
||
613 | /* |
||
614 | * Common platform init routine for all SPI NOR devices. |
||
615 | */ |
||
616 | static __init const struct rb_info *rbspi_platform_setup(void) |
||
617 | { |
||
618 | const struct rb_info *info; |
||
619 | char buf[RBSPI_MACH_BUFLEN] = "MikroTik "; |
||
620 | char *str; |
||
621 | int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1; |
||
622 | |||
623 | info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000); |
||
624 | if (!info) |
||
625 | return NULL; |
||
626 | |||
627 | if (info->board_name) { |
||
628 | str = "RouterBOARD "; |
||
629 | if (strncmp(info->board_name, str, strlen(str))) { |
||
630 | strncat(buf, str, len); |
||
631 | len -= strlen(str); |
||
632 | } |
||
633 | strncat(buf, info->board_name, len); |
||
634 | } |
||
635 | else |
||
636 | strncat(buf, "UNKNOWN", len); |
||
637 | |||
638 | mips_set_machine_name(buf); |
||
639 | |||
640 | /* fix partitions based on flash parsing */ |
||
641 | rbspi_init_partitions(info); |
||
642 | |||
643 | return info; |
||
644 | } |
||
645 | |||
646 | /* |
||
647 | * Common peripherals init routine for all SPI NOR devices. |
||
648 | * Sets SPI and USB. |
||
649 | */ |
||
650 | static void __init rbspi_peripherals_setup(u32 flags) |
||
651 | { |
||
652 | unsigned spi_n; |
||
653 | |||
654 | if (flags & RBSPI_HAS_SSR) |
||
655 | spi_n = ARRAY_SIZE(rbspi_spi_info); |
||
656 | else |
||
657 | spi_n = 1; /* only one device on bus0 */ |
||
658 | |||
659 | rbspi_ath79_spi_data.num_chipselect = spi_n; |
||
660 | rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios; |
||
661 | ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n); |
||
662 | |||
663 | if (flags & RBSPI_HAS_USB) |
||
664 | ath79_register_usb(); |
||
665 | |||
666 | if (flags & RBSPI_HAS_PCI) |
||
667 | ath79_register_pci(); |
||
668 | } |
||
669 | |||
670 | /* |
||
671 | * Common network init routine for all SPI NOR devices. |
||
672 | * Sets LAN/WAN/WLAN. |
||
673 | */ |
||
674 | static void __init rbspi_network_setup(u32 flags, int gmac1_offset, |
||
675 | int wmac0_offset, int wmac1_offset) |
||
676 | { |
||
677 | /* for QCA953x that will init mdio1_device/data */ |
||
678 | ath79_register_mdio(0, 0x0); |
||
679 | if (flags & RBSPI_HAS_MDIO1) |
||
680 | ath79_register_mdio(1, 0x0); |
||
681 | |||
682 | if (flags & RBSPI_HAS_WAN4) { |
||
683 | ath79_setup_ar934x_eth_cfg(0); |
||
684 | |||
685 | /* set switch to oper mode 1, PHY4 connected to CPU */ |
||
686 | ath79_switch_data.phy4_mii_en = 1; |
||
687 | ath79_switch_data.phy_poll_mask |= BIT(4); |
||
688 | |||
689 | /* init GMAC0 connected to PHY4 at 100M */ |
||
690 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
||
691 | ath79_eth0_data.phy_mask = BIT(4); |
||
692 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
||
693 | ath79_register_eth(0); |
||
694 | } else { |
||
695 | /* set the SoC to SW_ONLY_MODE, which connects all PHYs |
||
696 | * to the internal switch. |
||
697 | * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in |
||
698 | * the QCA953x, this works because this configuration bit is |
||
699 | * the same as the AR934x. There's no equivalent function for |
||
700 | * QCA953x for now. */ |
||
701 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE); |
||
702 | } |
||
703 | |||
704 | /* init GMAC1 */ |
||
705 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset); |
||
706 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
||
707 | ath79_register_eth(1); |
||
708 | |||
709 | if (flags & RBSPI_HAS_WLAN0) |
||
710 | rbspi_wlan_init(0, wmac0_offset); |
||
711 | |||
712 | if (flags & RBSPI_HAS_WLAN1) |
||
713 | rbspi_wlan_init(1, wmac1_offset); |
||
714 | } |
||
715 | |||
716 | static __init void rbspi_register_reset_button(int gpio) |
||
717 | { |
||
718 | rbspi_gpio_keys_reset[0].gpio = gpio; |
||
719 | ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL, |
||
720 | ARRAY_SIZE(rbspi_gpio_keys_reset), |
||
721 | rbspi_gpio_keys_reset); |
||
722 | } |
||
723 | |||
724 | /* |
||
725 | * Init the mAP lite hardware (QCA953x). |
||
726 | * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0. |
||
727 | * Trying to use GMAC0 in direct mode was unsucessful, so we're |
||
728 | * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal |
||
729 | * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused. |
||
730 | */ |
||
731 | static void __init rbmapl_setup(void) |
||
732 | { |
||
733 | u32 flags = RBSPI_HAS_WLAN0; |
||
734 | |||
735 | if (!rbspi_platform_setup()) |
||
736 | return; |
||
737 | |||
738 | rbspi_peripherals_setup(flags); |
||
739 | |||
740 | /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */ |
||
741 | rbspi_network_setup(flags, 0, 1, 0); |
||
742 | |||
743 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds); |
||
744 | |||
745 | /* mAP lite has a single reset button as gpio 16 */ |
||
746 | rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET); |
||
747 | |||
748 | /* clear internal multiplexing */ |
||
749 | ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO); |
||
750 | ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO); |
||
751 | } |
||
752 | |||
753 | /* |
||
754 | * Init the hAP lite hardware (QCA953x). |
||
755 | * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4 |
||
756 | * being assigned to LAN on the casing, and port 1 being assigned |
||
757 | * to "internet" (WAN) on the casing. Port 1 is connected to PHY3. |
||
758 | * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device. |
||
759 | */ |
||
760 | static void __init rbhapl_setup(void) |
||
761 | { |
||
762 | u32 flags = RBSPI_HAS_WLAN0; |
||
763 | |||
764 | if (!rbspi_platform_setup()) |
||
765 | return; |
||
766 | |||
767 | rbspi_peripherals_setup(flags); |
||
768 | |||
769 | /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */ |
||
770 | rbspi_network_setup(flags, 0, 4, 0); |
||
771 | |||
772 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds); |
||
773 | |||
774 | /* hAP lite has a single reset button as gpio 16 */ |
||
775 | rbspi_register_reset_button(RBHAPL_GPIO_BTN_RESET); |
||
776 | } |
||
777 | |||
778 | /* |
||
779 | * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform |
||
780 | */ |
||
781 | static void __init rbspi_952_750r2_setup(u32 flags) |
||
782 | { |
||
783 | if (flags & RBSPI_HAS_SSR) |
||
784 | rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS; |
||
785 | |||
786 | rbspi_peripherals_setup(flags); |
||
787 | |||
788 | /* |
||
789 | * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP), |
||
790 | * WLAN1 MAC IS HW MAC + 6 (hAP ac lite) |
||
791 | */ |
||
792 | rbspi_network_setup(flags, 1, 5, 6); |
||
793 | |||
794 | if (flags & RBSPI_HAS_USB) |
||
3 | office | 795 | gpio_request_one(RB952_GPIO_USB_POWER, |
1 | office | 796 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
3 | office | 797 | "USB power"); |
1 | office | 798 | |
799 | if (flags & RBSPI_HAS_POE) |
||
800 | gpio_request_one(RB952_GPIO_POE_POWER, |
||
801 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
||
802 | "POE power"); |
||
803 | |||
804 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds); |
||
805 | |||
806 | /* These devices have a single reset button as gpio 16 */ |
||
807 | rbspi_register_reset_button(RB952_GPIO_BTN_RESET); |
||
808 | } |
||
809 | |||
810 | /* |
||
811 | * Init the hAP (ac lite) hardware (QCA953x). |
||
812 | * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned |
||
813 | * to LAN on the casing, and port 1 being assigned to "internet" (WAN). |
||
814 | * Port 1 is connected to PHY4 (the ports are labelled in reverse physical |
||
815 | * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the |
||
816 | * internal switch for the LAN ports. |
||
817 | * The device also has USB, PoE output and an SSR used for LED multiplexing. |
||
818 | * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a |
||
819 | * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1. |
||
820 | */ |
||
821 | static void __init rb952_setup(void) |
||
822 | { |
||
823 | u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB | |
||
824 | RBSPI_HAS_SSR | RBSPI_HAS_POE; |
||
825 | |||
826 | if (!rbspi_platform_setup()) |
||
827 | return; |
||
828 | |||
829 | /* differentiate the hAP from the hAP ac lite */ |
||
830 | if (strstr(mips_get_machine_name(), "952Ui-5ac2nD")) |
||
831 | flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI; |
||
832 | else |
||
833 | flags |= RBSPI_HAS_WLAN0; |
||
834 | |||
835 | rbspi_952_750r2_setup(flags); |
||
836 | } |
||
837 | |||
838 | /* |
||
839 | * Init the hEX (PoE) lite hardware (QCA953x). |
||
840 | * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without |
||
841 | * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only |
||
842 | * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE |
||
843 | * lite, only without USB. It shares the same bootloader board identifier. |
||
844 | */ |
||
845 | static void __init rb750upr2_setup(void) |
||
846 | { |
||
847 | u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR; |
||
848 | |||
849 | if (!rbspi_platform_setup()) |
||
850 | return; |
||
851 | |||
852 | /* differentiate the hEX lite from the hEX PoE lite */ |
||
853 | if (strstr(mips_get_machine_name(), "750UP r2")) |
||
854 | flags |= RBSPI_HAS_USB | RBSPI_HAS_POE; |
||
855 | |||
856 | /* differentiate the Powerbox from the hEX lite */ |
||
857 | else if (strstr(mips_get_machine_name(), "750P r2")) |
||
858 | flags |= RBSPI_HAS_POE; |
||
859 | |||
860 | rbspi_952_750r2_setup(flags); |
||
861 | } |
||
862 | |||
863 | /* |
||
864 | * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558). |
||
865 | * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is |
||
866 | * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the |
||
867 | * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order. |
||
868 | * The SFP cage is not assigned by default on RouterOS. Extra work is required |
||
869 | * to support this interface as it is directly connected to the SoC (eth1). |
||
870 | * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio |
||
871 | * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however |
||
872 | * they are not attached to GPIOs, extra work is required to support these. |
||
873 | * PoE and USB output power control is supported. |
||
874 | */ |
||
875 | static void __init rb962_setup(void) |
||
876 | { |
||
877 | u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI; |
||
878 | |||
879 | if (!rbspi_platform_setup()) |
||
880 | return; |
||
881 | |||
882 | rbspi_peripherals_setup(flags); |
||
883 | |||
884 | /* Do not call rbspi_network_setup as we have a discrete switch chip */ |
||
885 | ath79_eth0_pll_data.pll_1000 = 0xae000000; |
||
886 | ath79_eth0_pll_data.pll_100 = 0xa0000101; |
||
887 | ath79_eth0_pll_data.pll_10 = 0xa0001313; |
||
888 | |||
889 | ath79_register_mdio(0, 0x0); |
||
890 | mdiobus_register_board_info(rb962_mdio0_info, |
||
891 | ARRAY_SIZE(rb962_mdio0_info)); |
||
892 | |||
893 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
||
894 | |||
895 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
||
896 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
||
897 | ath79_eth0_data.phy_mask = BIT(0); |
||
898 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
||
899 | ath79_register_eth(0); |
||
900 | |||
901 | /* WLAN1 MAC is HW MAC + 7 */ |
||
902 | rbspi_wlan_init(1, 7); |
||
903 | |||
904 | if (flags & RBSPI_HAS_USB) |
||
3 | office | 905 | gpio_request_one(RB962_GPIO_USB_POWER, |
1 | office | 906 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
3 | office | 907 | "USB power"); |
1 | office | 908 | |
909 | /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */ |
||
910 | if (flags & RBSPI_HAS_POE) |
||
911 | gpio_request_one(RB962_GPIO_POE_POWER, |
||
912 | GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW | |
||
913 | GPIOF_EXPORT_DIR_FIXED, |
||
914 | "POE power"); |
||
915 | |||
916 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio), |
||
917 | rb962_leds_gpio); |
||
918 | |||
919 | /* This device has a single reset button as gpio 20 */ |
||
920 | rbspi_register_reset_button(RB962_GPIO_BTN_RESET); |
||
921 | } |
||
922 | |||
923 | /* |
||
924 | * Init the LHG hardware (AR9344). |
||
925 | * The LHG 5nD has a single ethernet port connected to PHY0. |
||
926 | * Wireless is provided via 5GHz WLAN1. |
||
927 | */ |
||
928 | static void __init rblhg_setup(void) |
||
929 | { |
||
930 | u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1; |
||
931 | |||
932 | if (!rbspi_platform_setup()) |
||
933 | return; |
||
934 | |||
935 | rbspi_peripherals_setup(flags); |
||
936 | |||
937 | /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */ |
||
938 | rbspi_network_setup(flags, 0, 0, 1); |
||
939 | |||
940 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds); |
||
941 | |||
942 | rbspi_register_reset_button(RBLHG_GPIO_BTN_RESET); |
||
943 | } |
||
944 | |||
945 | /* |
||
946 | * Init the wAP hardware. |
||
947 | * The wAP 2nD has a single ethernet port. |
||
948 | */ |
||
949 | static void __init rbwap_setup(void) |
||
950 | { |
||
951 | u32 flags = RBSPI_HAS_WLAN0; |
||
952 | |||
953 | if (!rbspi_platform_setup()) |
||
954 | return; |
||
955 | |||
956 | rbspi_peripherals_setup(flags); |
||
957 | |||
958 | /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */ |
||
959 | rbspi_network_setup(flags, 0, 1, 0); |
||
960 | |||
961 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds); |
||
962 | |||
963 | /* wAP has a single reset button as GPIO 16 */ |
||
964 | rbspi_register_reset_button(RBWAP_GPIO_BTN_RESET); |
||
965 | } |
||
966 | |||
967 | /* |
||
968 | * Init the cAP hardware (EXPERIMENTAL). |
||
969 | * The cAP 2nD has a single ethernet port, and a global LED switch. |
||
970 | */ |
||
971 | static void __init rbcap_setup(void) |
||
972 | { |
||
973 | u32 flags = RBSPI_HAS_WLAN0; |
||
974 | |||
975 | if (!rbspi_platform_setup()) |
||
976 | return; |
||
977 | |||
978 | rbspi_peripherals_setup(flags); |
||
979 | |||
980 | /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */ |
||
981 | rbspi_network_setup(flags, 0, 1, 0); |
||
982 | |||
983 | gpio_request_one(RBCAP_GPIO_LED_ALL, |
||
984 | GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED, |
||
985 | "LEDs enable"); |
||
986 | |||
987 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds); |
||
988 | } |
||
989 | |||
990 | /* |
||
991 | * Init the mAP hardware. |
||
992 | * The mAP 2nD has two ethernet ports, PoE output, SSR for LED |
||
993 | * multiplexing and USB port. |
||
994 | */ |
||
995 | static void __init rbmap_setup(void) |
||
996 | { |
||
997 | u32 flags = RBSPI_HAS_USB | RBSPI_HAS_WLAN0 | |
||
998 | RBSPI_HAS_SSR | RBSPI_HAS_POE; |
||
999 | |||
1000 | if (!rbspi_platform_setup()) |
||
1001 | return; |
||
1002 | |||
1003 | rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS; |
||
1004 | rbspi_peripherals_setup(flags); |
||
1005 | |||
1006 | /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */ |
||
1007 | rbspi_network_setup(flags, 0, 2, 0); |
||
1008 | |||
1009 | if (flags & RBSPI_HAS_POE) |
||
1010 | gpio_request_one(RBMAP_GPIO_POE_POWER, |
||
1011 | GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED, |
||
1012 | "POE power"); |
||
1013 | |||
3 | office | 1014 | /* USB power GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */ |
1 | office | 1015 | if (flags & RBSPI_HAS_USB) |
3 | office | 1016 | gpio_request_one(RBMAP_GPIO_USB_POWER, |
1 | office | 1017 | GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW | |
1018 | GPIOF_EXPORT_DIR_FIXED, |
||
3 | office | 1019 | "USB power"); |
1 | office | 1020 | |
1021 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds); |
||
1022 | |||
1023 | /* mAP 2nD has a single reset button as gpio 16 */ |
||
1024 | rbspi_register_reset_button(RBMAP_GPIO_BTN_RESET); |
||
1025 | } |
||
1026 | |||
1027 | /* |
||
1028 | * Init the wAPGSC (RB wAPG-5HacT2HnD // wAP AC) hardware. |
||
1029 | * The wAPGSC has one Ethernet port via AR8033 with PoE input, dual radio (SoC |
||
1030 | * 2.4 GHz and external QCA9880) and a ZT2046Q temperature and voltage sensor |
||
1031 | * (currently not supported). |
||
1032 | */ |
||
1033 | static void __init rbwapgsc_setup(void) |
||
1034 | { |
||
1035 | u32 flags = RBSPI_HAS_PCI; |
||
1036 | |||
1037 | if (!rbspi_platform_setup()) |
||
1038 | return; |
||
1039 | |||
1040 | rbspi_peripherals_setup(flags); |
||
1041 | |||
1042 | platform_device_register(&rbwapgsc_phy_device); |
||
1043 | |||
1044 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); |
||
1045 | ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev; |
||
1046 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
||
1047 | ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR); |
||
1048 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
||
1049 | ath79_eth1_pll_data.pll_100 = 0x80000101; |
||
1050 | ath79_eth1_pll_data.pll_10 = 0x80001313; |
||
1051 | ath79_eth1_data.speed = SPEED_1000; |
||
1052 | ath79_eth1_data.duplex = DUPLEX_FULL; |
||
1053 | ath79_register_eth(1); |
||
1054 | |||
1055 | rbspi_wlan_init(1, 2); |
||
1056 | |||
1057 | rbspi_register_reset_button(RBWAPGSC_GPIO_BTN_RESET); |
||
1058 | |||
1059 | ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE| |
||
1060 | QCA955X_GPIO_REG_OUT_FUNC4| |
||
1061 | QCA955X_GPIO_REG_OUT_FUNC3); |
||
1062 | |||
1063 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwapgsc_leds), |
||
1064 | rbwapgsc_leds); |
||
1065 | } |
||
1066 | |||
1067 | /* |
||
1068 | * Setup the 911L hardware (AR9344). |
||
1069 | */ |
||
1070 | static void __init rb911l_setup(void) |
||
1071 | { |
||
1072 | const struct rb_info *info; |
||
1073 | |||
1074 | info = rbspi_platform_setup(); |
||
1075 | if (!info) |
||
1076 | return; |
||
1077 | |||
1078 | if (!rb_has_hw_option(info, RB_HW_OPT_NO_NAND)) { |
||
1079 | /* |
||
1080 | * Old hardware revisions might be equipped with a NAND flash |
||
1081 | * chip instead of the 16MiB SPI NOR device. Those boards are |
||
1082 | * not supported at the moment, so throw a warning and skip |
||
1083 | * the peripheral setup to avoid messing up the data in the |
||
1084 | * flash chip. |
||
1085 | */ |
||
1086 | WARN(1, "The NAND flash on this board is not supported.\n"); |
||
1087 | } else { |
||
1088 | rbspi_peripherals_setup(0); |
||
1089 | } |
||
1090 | |||
1091 | ath79_register_mdio(1, 0x0); |
||
1092 | |||
1093 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0); |
||
1094 | |||
1095 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
||
1096 | ath79_eth1_data.speed = SPEED_1000; |
||
1097 | ath79_eth1_data.duplex = DUPLEX_FULL; |
||
1098 | |||
1099 | ath79_register_eth(1); |
||
1100 | |||
1101 | rbspi_wlan_init(0, 1); |
||
1102 | |||
1103 | rbspi_register_reset_button(RB911L_GPIO_BTN_RESET); |
||
1104 | |||
1105 | /* Make the eth LED controllable by software. */ |
||
1106 | ath79_gpio_output_select(RB911L_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO); |
||
1107 | |||
1108 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb911l_leds), rb911l_leds); |
||
1109 | } |
||
1110 | |||
1111 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup); |
||
1112 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup); |
||
1113 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_911L, "911L", rb911l_setup); |
||
1114 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup); |
||
1115 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup); |
||
1116 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup); |
||
1117 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup); |
||
1118 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup); |
||
1119 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup); |
||
1120 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup); |
||
1121 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPAC, "wapg-sc", rbwapgsc_setup); |