OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * MikroTik RouterBOARD 91X support |
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3 | * |
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4 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU General Public License version 2 as published |
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8 | * by the Free Software Foundation. |
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9 | */ |
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10 | |||
11 | #define pr_fmt(fmt) "rb91x: " fmt |
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12 | |||
13 | #include <linux/phy.h> |
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14 | #include <linux/delay.h> |
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15 | #include <linux/platform_device.h> |
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16 | #include <linux/ath9k_platform.h> |
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17 | #include <linux/mtd/mtd.h> |
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18 | #include <linux/mtd/nand.h> |
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19 | #include <linux/mtd/partitions.h> |
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20 | #include <linux/spi/spi.h> |
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21 | #include <linux/spi/74x164.h> |
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22 | #include <linux/spi/flash.h> |
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23 | #include <linux/routerboot.h> |
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24 | #include <linux/gpio.h> |
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25 | #include <linux/platform_data/gpio-latch.h> |
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26 | #include <linux/platform_data/rb91x_nand.h> |
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27 | #include <linux/platform_data/phy-at803x.h> |
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28 | |||
29 | #include <asm/prom.h> |
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30 | #include <asm/mach-ath79/ath79.h> |
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31 | #include <asm/mach-ath79/ath79_spi_platform.h> |
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32 | #include <asm/mach-ath79/ar71xx_regs.h> |
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33 | |||
34 | #include "common.h" |
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35 | #include "dev-eth.h" |
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36 | #include "dev-leds-gpio.h" |
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37 | #include "dev-nfc.h" |
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38 | #include "dev-usb.h" |
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39 | #include "dev-spi.h" |
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40 | #include "dev-wmac.h" |
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41 | #include "machtypes.h" |
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42 | #include "pci.h" |
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43 | #include "routerboot.h" |
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44 | |||
45 | #define RB_ROUTERBOOT_OFFSET 0x0000 |
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46 | #define RB_ROUTERBOOT_MIN_SIZE 0xb000 |
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47 | #define RB_HARD_CFG_SIZE 0x1000 |
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48 | #define RB_BIOS_OFFSET 0xd000 |
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49 | #define RB_BIOS_SIZE 0x1000 |
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50 | #define RB_SOFT_CFG_OFFSET 0xf000 |
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51 | #define RB_SOFT_CFG_SIZE 0x1000 |
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52 | |||
53 | #define RB91X_FLAG_USB BIT(0) |
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54 | #define RB91X_FLAG_PCIE BIT(1) |
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55 | |||
56 | #define RB91X_LATCH_GPIO_BASE 32 |
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57 | #define RB91X_LATCH_GPIO(_x) (RB91X_LATCH_GPIO_BASE + (_x)) |
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58 | |||
59 | #define RB91X_SSR_GPIO_BASE (RB91X_LATCH_GPIO_BASE + AR934X_GPIO_COUNT) |
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60 | #define RB91X_SSR_GPIO(_x) (RB91X_SSR_GPIO_BASE + (_x)) |
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61 | |||
62 | #define RB91X_SSR_BIT_LED1 0 |
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63 | #define RB91X_SSR_BIT_LED2 1 |
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64 | #define RB91X_SSR_BIT_LED3 2 |
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65 | #define RB91X_SSR_BIT_LED4 3 |
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66 | #define RB91X_SSR_BIT_LED5 4 |
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67 | #define RB91X_SSR_BIT_5 5 |
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68 | #define RB91X_SSR_BIT_USB_POWER 6 |
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69 | #define RB91X_SSR_BIT_PCIE_POWER 7 |
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70 | |||
71 | #define RB91X_GPIO_SSR_STROBE RB91X_LATCH_GPIO(0) |
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72 | #define RB91X_GPIO_LED_POWER RB91X_LATCH_GPIO(1) |
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73 | #define RB91X_GPIO_LED_USER RB91X_LATCH_GPIO(2) |
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74 | #define RB91X_GPIO_NAND_READ RB91X_LATCH_GPIO(3) |
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75 | #define RB91X_GPIO_NAND_RDY RB91X_LATCH_GPIO(4) |
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76 | #define RB91X_GPIO_NLE RB91X_LATCH_GPIO(11) |
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77 | #define RB91X_GPIO_NAND_NRW RB91X_LATCH_GPIO(12) |
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78 | #define RB91X_GPIO_NAND_NCE RB91X_LATCH_GPIO(13) |
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79 | #define RB91X_GPIO_NAND_CLE RB91X_LATCH_GPIO(14) |
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80 | #define RB91X_GPIO_NAND_ALE RB91X_LATCH_GPIO(15) |
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81 | |||
82 | #define RB91X_GPIO_LED_1 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED1) |
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83 | #define RB91X_GPIO_LED_2 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED2) |
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84 | #define RB91X_GPIO_LED_3 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED3) |
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85 | #define RB91X_GPIO_LED_4 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED4) |
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86 | #define RB91X_GPIO_LED_5 RB91X_SSR_GPIO(RB91X_SSR_BIT_LED5) |
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87 | #define RB91X_GPIO_USB_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_USB_POWER) |
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88 | #define RB91X_GPIO_PCIE_POWER RB91X_SSR_GPIO(RB91X_SSR_BIT_PCIE_POWER) |
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89 | |||
90 | struct rb_board_info { |
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91 | const char *name; |
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92 | u32 flags; |
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93 | }; |
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94 | |||
95 | static struct mtd_partition rb711gr100_spi_partitions[] = { |
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96 | { |
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97 | .name = "routerboot", |
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98 | .offset = RB_ROUTERBOOT_OFFSET, |
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99 | .mask_flags = MTD_WRITEABLE, |
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100 | }, { |
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101 | .name = "hard_config", |
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102 | .size = RB_HARD_CFG_SIZE, |
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103 | .mask_flags = MTD_WRITEABLE, |
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104 | }, { |
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105 | .name = "bios", |
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106 | .offset = RB_BIOS_OFFSET, |
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107 | .size = RB_BIOS_SIZE, |
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108 | .mask_flags = MTD_WRITEABLE, |
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109 | }, { |
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110 | .name = "soft_config", |
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111 | .size = RB_SOFT_CFG_SIZE, |
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112 | } |
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113 | }; |
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114 | |||
115 | static struct flash_platform_data rb711gr100_spi_flash_data = { |
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116 | .parts = rb711gr100_spi_partitions, |
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117 | .nr_parts = ARRAY_SIZE(rb711gr100_spi_partitions), |
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118 | }; |
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119 | |||
120 | static int rb711gr100_gpio_latch_gpios[AR934X_GPIO_COUNT] __initdata = { |
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121 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, |
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122 | 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 |
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123 | }; |
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124 | |||
125 | static struct gpio_latch_platform_data rb711gr100_gpio_latch_data __initdata = { |
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126 | .base = RB91X_LATCH_GPIO_BASE, |
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127 | .num_gpios = ARRAY_SIZE(rb711gr100_gpio_latch_gpios), |
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128 | .gpios = rb711gr100_gpio_latch_gpios, |
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129 | .le_gpio_index = 11, |
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130 | .le_active_low = true, |
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131 | }; |
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132 | |||
133 | static struct rb91x_nand_platform_data rb711gr100_nand_data __initdata = { |
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134 | .gpio_nce = RB91X_GPIO_NAND_NCE, |
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135 | .gpio_ale = RB91X_GPIO_NAND_ALE, |
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136 | .gpio_cle = RB91X_GPIO_NAND_CLE, |
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137 | .gpio_rdy = RB91X_GPIO_NAND_RDY, |
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138 | .gpio_read = RB91X_GPIO_NAND_READ, |
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139 | .gpio_nrw = RB91X_GPIO_NAND_NRW, |
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140 | .gpio_nle = RB91X_GPIO_NLE, |
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141 | }; |
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142 | |||
143 | static u8 rb711gr100_ssr_initdata[] = { |
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144 | BIT(RB91X_SSR_BIT_PCIE_POWER) | |
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145 | BIT(RB91X_SSR_BIT_USB_POWER) | |
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146 | BIT(RB91X_SSR_BIT_5) |
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147 | }; |
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148 | |||
149 | static struct gen_74x164_chip_platform_data rb711gr100_ssr_data = { |
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150 | .base = RB91X_SSR_GPIO_BASE, |
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151 | .num_registers = ARRAY_SIZE(rb711gr100_ssr_initdata), |
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152 | .init_data = rb711gr100_ssr_initdata, |
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153 | }; |
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154 | |||
155 | static struct spi_board_info rb711gr100_spi_info[] = { |
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156 | { |
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157 | .bus_num = 0, |
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158 | .chip_select = 0, |
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159 | .max_speed_hz = 25000000, |
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160 | .modalias = "m25p80", |
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161 | .platform_data = &rb711gr100_spi_flash_data, |
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162 | }, { |
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163 | .bus_num = 0, |
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164 | .chip_select = 1, |
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165 | .max_speed_hz = 10000000, |
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166 | .modalias = "74x164", |
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167 | .platform_data = &rb711gr100_ssr_data, |
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168 | } |
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169 | }; |
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170 | |||
171 | static int rb711gr100_spi_cs_gpios[2] = { |
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172 | -ENOENT, |
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173 | RB91X_GPIO_SSR_STROBE, |
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174 | }; |
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175 | |||
176 | static struct ath79_spi_platform_data rb711gr100_spi_data __initdata = { |
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177 | .bus_num = 0, |
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178 | .num_chipselect = 2, |
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179 | .cs_gpios = rb711gr100_spi_cs_gpios, |
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180 | }; |
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181 | |||
182 | static struct gpio_led rb711gr100_leds[] __initdata = { |
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183 | { |
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184 | .name = "rb:green:led1", |
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185 | .gpio = RB91X_GPIO_LED_1, |
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186 | .active_low = 0, |
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187 | }, |
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188 | { |
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189 | .name = "rb:green:led2", |
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190 | .gpio = RB91X_GPIO_LED_2, |
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191 | .active_low = 0, |
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192 | }, |
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193 | { |
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194 | .name = "rb:green:led3", |
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195 | .gpio = RB91X_GPIO_LED_3, |
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196 | .active_low = 0, |
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197 | }, |
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198 | { |
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199 | .name = "rb:green:led4", |
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200 | .gpio = RB91X_GPIO_LED_4, |
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201 | .active_low = 0, |
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202 | }, |
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203 | { |
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204 | .name = "rb:green:led5", |
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205 | .gpio = RB91X_GPIO_LED_5, |
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206 | .active_low = 0, |
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207 | }, |
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208 | { |
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209 | .name = "rb:green:user", |
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210 | .gpio = RB91X_GPIO_LED_USER, |
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211 | .active_low = 0, |
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212 | }, |
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213 | { |
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214 | .name = "rb:green:power", |
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215 | .gpio = RB91X_GPIO_LED_POWER, |
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216 | .active_low = 0, |
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3 | office | 217 | .default_state = LEDS_GPIO_DEFSTATE_KEEP, |
1 | office | 218 | }, |
219 | }; |
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220 | |||
221 | static struct at803x_platform_data rb91x_at803x_data = { |
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222 | .disable_smarteee = 1, |
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223 | .enable_rgmii_rx_delay = 1, |
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224 | .enable_rgmii_tx_delay = 1, |
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225 | }; |
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226 | |||
227 | static struct mdio_board_info rb91x_mdio0_info[] = { |
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228 | { |
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229 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 230 | .phy_addr = 0, |
1 | office | 231 | .platform_data = &rb91x_at803x_data, |
232 | }, |
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233 | }; |
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234 | |||
235 | static void __init rb711gr100_init_partitions(const struct rb_info *info) |
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236 | { |
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237 | rb711gr100_spi_partitions[0].size = info->hard_cfg_offs; |
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238 | rb711gr100_spi_partitions[1].offset = info->hard_cfg_offs; |
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239 | |||
240 | rb711gr100_spi_partitions[3].offset = info->soft_cfg_offs; |
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241 | } |
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242 | |||
243 | void __init rb711gr100_wlan_init(void) |
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244 | { |
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245 | char *caldata; |
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246 | u8 wlan_mac[ETH_ALEN]; |
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247 | |||
248 | caldata = rb_get_wlan_data(); |
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249 | if (caldata == NULL) |
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250 | return; |
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251 | |||
252 | ath79_init_mac(wlan_mac, ath79_mac_base, 1); |
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253 | ath79_register_wmac(caldata + 0x1000, wlan_mac); |
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254 | |||
255 | kfree(caldata); |
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256 | } |
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257 | |||
258 | #define RB_BOARD_INFO(_name, _flags) \ |
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259 | { \ |
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260 | .name = (_name), \ |
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261 | .flags = (_flags), \ |
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262 | } |
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263 | |||
264 | static const struct rb_board_info rb711gr100_boards[] __initconst = { |
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265 | RB_BOARD_INFO("911G-2HPnD", 0), |
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266 | RB_BOARD_INFO("911G-5HPnD", 0), |
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267 | RB_BOARD_INFO("912UAG-2HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), |
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268 | RB_BOARD_INFO("912UAG-5HPnD", RB91X_FLAG_USB | RB91X_FLAG_PCIE), |
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269 | }; |
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270 | |||
271 | static u32 rb711gr100_get_flags(const struct rb_info *info) |
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272 | { |
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273 | int i; |
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274 | |||
275 | for (i = 0; i < ARRAY_SIZE(rb711gr100_boards); i++) { |
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276 | const struct rb_board_info *bi; |
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277 | |||
278 | bi = &rb711gr100_boards[i]; |
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279 | if (strcmp(info->board_name, bi->name) == 0) |
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280 | return bi->flags; |
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281 | } |
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282 | |||
283 | return 0; |
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284 | } |
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285 | |||
286 | static void __init rb711gr100_setup(void) |
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287 | { |
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288 | const struct rb_info *info; |
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289 | char buf[64]; |
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290 | u32 flags; |
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291 | |||
292 | info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000); |
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293 | if (!info) |
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294 | return; |
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295 | |||
296 | scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s", |
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297 | (info->board_name) ? info->board_name : ""); |
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298 | mips_set_machine_name(buf); |
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299 | |||
300 | rb711gr100_init_partitions(info); |
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301 | ath79_register_spi(&rb711gr100_spi_data, rb711gr100_spi_info, |
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302 | ARRAY_SIZE(rb711gr100_spi_info)); |
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303 | |||
304 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | |
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305 | AR934X_ETH_CFG_RXD_DELAY | |
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306 | AR934X_ETH_CFG_SW_ONLY_MODE); |
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307 | |||
308 | ath79_register_mdio(0, 0x0); |
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309 | |||
310 | mdiobus_register_board_info(rb91x_mdio0_info, |
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311 | ARRAY_SIZE(rb91x_mdio0_info)); |
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312 | |||
313 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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314 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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315 | ath79_eth0_data.phy_mask = BIT(0); |
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316 | ath79_eth0_pll_data.pll_1000 = 0x02000000; |
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317 | |||
318 | ath79_register_eth(0); |
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319 | |||
320 | rb711gr100_wlan_init(); |
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321 | |||
322 | platform_device_register_data(NULL, "rb91x-nand", -1, |
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323 | &rb711gr100_nand_data, |
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324 | sizeof(rb711gr100_nand_data)); |
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325 | |||
326 | platform_device_register_data(NULL, "gpio-latch", -1, |
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327 | &rb711gr100_gpio_latch_data, |
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328 | sizeof(rb711gr100_gpio_latch_data)); |
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329 | |||
330 | ath79_register_leds_gpio(-1, ARRAY_SIZE(rb711gr100_leds), |
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331 | rb711gr100_leds); |
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332 | |||
333 | flags = rb711gr100_get_flags(info); |
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334 | |||
335 | if (flags & RB91X_FLAG_USB) |
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336 | ath79_register_usb(); |
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337 | |||
338 | if (flags & RB91X_FLAG_PCIE) |
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339 | ath79_register_pci(); |
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340 | |||
341 | } |
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342 | |||
343 | MIPS_MACHINE_NONAME(ATH79_MACH_RB_711GR100, "711Gr100", rb711gr100_setup); |