OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Atheros PB42 board support |
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3 | * |
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4 | * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org> |
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5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #include <asm/mach-ath79/ath79.h> |
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13 | |||
14 | #include "dev-eth.h" |
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15 | #include "dev-gpio-buttons.h" |
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16 | #include "dev-m25p80.h" |
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17 | #include "dev-usb.h" |
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18 | #include "machtypes.h" |
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19 | #include "pci.h" |
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20 | |||
21 | #define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ |
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22 | #define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) |
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23 | |||
24 | #define PB42_GPIO_BTN_SW4 8 |
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25 | #define PB42_GPIO_BTN_SW5 3 |
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26 | |||
27 | static struct gpio_keys_button pb42_gpio_keys[] __initdata = { |
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28 | { |
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29 | .desc = "sw4", |
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30 | .type = EV_KEY, |
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31 | .code = BTN_0, |
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32 | .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, |
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33 | .gpio = PB42_GPIO_BTN_SW4, |
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34 | .active_low = 1, |
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35 | }, { |
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36 | .desc = "sw5", |
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37 | .type = EV_KEY, |
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38 | .code = BTN_1, |
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39 | .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, |
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40 | .gpio = PB42_GPIO_BTN_SW5, |
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41 | .active_low = 1, |
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42 | } |
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43 | }; |
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44 | |||
45 | static const char *pb42_part_probes[] = { |
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46 | "RedBoot", |
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47 | NULL, |
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48 | }; |
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49 | |||
50 | static struct flash_platform_data pb42_flash_data = { |
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51 | .part_probes = pb42_part_probes, |
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52 | }; |
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53 | |||
54 | #define PB42_WAN_PHYMASK BIT(20) |
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55 | #define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) |
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56 | #define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) |
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57 | |||
58 | static void __init pb42_init(void) |
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59 | { |
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60 | ath79_register_m25p80(&pb42_flash_data); |
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61 | |||
62 | ath79_register_mdio(0, ~PB42_MDIO_PHYMASK); |
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63 | |||
64 | ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0); |
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65 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; |
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66 | ath79_eth0_data.phy_mask = PB42_WAN_PHYMASK; |
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67 | |||
68 | ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1); |
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69 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; |
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70 | ath79_eth1_data.speed = SPEED_100; |
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71 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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72 | |||
73 | ath79_register_eth(0); |
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74 | ath79_register_eth(1); |
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75 | |||
76 | ath79_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, |
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77 | ARRAY_SIZE(pb42_gpio_keys), |
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78 | pb42_gpio_keys); |
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79 | |||
80 | ath79_register_pci(); |
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81 | } |
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82 | |||
83 | MIPS_MACHINE(ATH79_MACH_PB42, "PB42", "Atheros PB42", pb42_init); |