OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * OpenMesh OM5P-AC support |
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3 | * |
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4 | * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com> |
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5 | * Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or modify it |
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8 | * under the terms of the GNU General Public License version 2 as published |
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9 | * by the Free Software Foundation. |
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10 | */ |
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11 | |||
12 | #include <linux/gpio.h> |
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13 | #include <linux/mtd/mtd.h> |
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14 | #include <linux/mtd/partitions.h> |
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15 | #include <linux/platform_device.h> |
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16 | #include <linux/i2c.h> |
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17 | #include <linux/i2c-algo-bit.h> |
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18 | #include <linux/i2c-gpio.h> |
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19 | #include <linux/platform_data/phy-at803x.h> |
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20 | |||
21 | #include <asm/mach-ath79/ar71xx_regs.h> |
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22 | #include <asm/mach-ath79/ath79.h> |
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23 | |||
24 | #include "common.h" |
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25 | #include "dev-ap9x-pci.h" |
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26 | #include "dev-eth.h" |
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27 | #include "dev-leds-gpio.h" |
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28 | #include "dev-m25p80.h" |
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29 | #include "dev-wmac.h" |
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30 | #include "machtypes.h" |
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31 | #include "pci.h" |
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32 | |||
33 | #define OM5PAC_GPIO_LED_POWER 18 |
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34 | #define OM5PAC_GPIO_LED_GREEN 21 |
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35 | #define OM5PAC_GPIO_LED_RED 23 |
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36 | #define OM5PAC_GPIO_LED_YELLOW 22 |
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37 | #define OM5PAC_GPIO_LED_LAN 20 |
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38 | #define OM5PAC_GPIO_LED_WAN 19 |
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39 | #define OM5PAC_GPIO_I2C_SCL 12 |
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40 | #define OM5PAC_GPIO_I2C_SDA 11 |
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41 | |||
42 | #define OM5PAC_KEYS_POLL_INTERVAL 20 /* msecs */ |
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43 | #define OM5PAC_KEYS_DEBOUNCE_INTERVAL (3 * OM5PAC_KEYS_POLL_INTERVAL) |
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44 | |||
45 | #define OM5PAC_WMAC_CALDATA_OFFSET 0x1000 |
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46 | |||
47 | static struct gpio_led om5pac_leds_gpio[] __initdata = { |
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48 | { |
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49 | .name = "om5pac:blue:power", |
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50 | .gpio = OM5PAC_GPIO_LED_POWER, |
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51 | .active_low = 1, |
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52 | }, { |
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53 | .name = "om5pac:red:wifi", |
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54 | .gpio = OM5PAC_GPIO_LED_RED, |
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55 | .active_low = 1, |
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56 | }, { |
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57 | .name = "om5pac:yellow:wifi", |
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58 | .gpio = OM5PAC_GPIO_LED_YELLOW, |
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59 | .active_low = 1, |
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60 | }, { |
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61 | .name = "om5pac:green:wifi", |
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62 | .gpio = OM5PAC_GPIO_LED_GREEN, |
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63 | .active_low = 1, |
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64 | }, { |
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65 | .name = "om5pac:blue:lan", |
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66 | .gpio = OM5PAC_GPIO_LED_LAN, |
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67 | .active_low = 1, |
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68 | }, { |
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69 | .name = "om5pac:blue:wan", |
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70 | .gpio = OM5PAC_GPIO_LED_WAN, |
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71 | .active_low = 1, |
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72 | } |
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73 | }; |
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74 | |||
75 | static struct flash_platform_data om5pac_flash_data = { |
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76 | .type = "mx25l12805d", |
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77 | }; |
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78 | |||
79 | static struct i2c_gpio_platform_data om5pac_i2c_device_platdata = { |
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80 | .sda_pin = OM5PAC_GPIO_I2C_SDA, |
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81 | .scl_pin = OM5PAC_GPIO_I2C_SCL, |
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82 | .udelay = 10, |
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83 | .sda_is_open_drain = 1, |
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84 | .scl_is_open_drain = 1, |
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85 | }; |
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86 | |||
87 | static struct platform_device om5pac_i2c_device = { |
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88 | .name = "i2c-gpio", |
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89 | .id = 0, |
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90 | .dev = { |
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91 | .platform_data = &om5pac_i2c_device_platdata, |
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92 | }, |
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93 | }; |
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94 | |||
95 | static struct i2c_board_info om5pac_i2c_devs[] __initdata = { |
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96 | { |
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97 | I2C_BOARD_INFO("tmp423", 0x4c), |
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98 | }, |
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99 | }; |
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100 | |||
101 | static struct at803x_platform_data om5pac_at803x_data = { |
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102 | .disable_smarteee = 1, |
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103 | .enable_rgmii_rx_delay = 1, |
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104 | .enable_rgmii_tx_delay = 1, |
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105 | }; |
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106 | |||
107 | static struct mdio_board_info om5pac_mdio0_info[] = { |
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108 | { |
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109 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 110 | .phy_addr = 1, |
1 | office | 111 | .platform_data = &om5pac_at803x_data, |
112 | }, |
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113 | { |
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114 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 115 | .phy_addr = 2, |
1 | office | 116 | .platform_data = &om5pac_at803x_data, |
117 | }, |
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118 | }; |
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119 | |||
120 | static void __init om5p_ac_setup_qca955x_eth_cfg(u32 mask, |
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121 | unsigned int rxd, |
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122 | unsigned int rxdv, |
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123 | unsigned int txd, |
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124 | unsigned int txe) |
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125 | { |
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126 | void __iomem *base; |
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127 | u32 t; |
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128 | |||
129 | base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); |
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130 | |||
131 | t = mask; |
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132 | t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT; |
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133 | t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT; |
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134 | t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; |
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135 | t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; |
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136 | |||
137 | __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); |
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138 | |||
139 | iounmap(base); |
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140 | } |
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141 | |||
142 | static void __init om5p_ac_setup(void) |
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143 | { |
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144 | u8 *art = (u8 *)KSEG1ADDR(0x1fff0000); |
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145 | u8 mac[6]; |
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146 | |||
147 | /* temperature sensor */ |
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148 | platform_device_register(&om5pac_i2c_device); |
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149 | i2c_register_board_info(0, om5pac_i2c_devs, |
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150 | ARRAY_SIZE(om5pac_i2c_devs)); |
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151 | |||
152 | ath79_gpio_output_select(OM5PAC_GPIO_LED_WAN, QCA955X_GPIO_OUT_GPIO); |
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153 | |||
154 | ath79_register_m25p80(&om5pac_flash_data); |
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155 | ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pac_leds_gpio), |
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156 | om5pac_leds_gpio); |
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157 | |||
158 | ath79_init_mac(mac, art, 0x02); |
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159 | ath79_register_wmac(art + OM5PAC_WMAC_CALDATA_OFFSET, mac); |
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160 | |||
161 | om5p_ac_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0); |
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162 | ath79_register_mdio(0, 0x0); |
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163 | |||
164 | mdiobus_register_board_info(om5pac_mdio0_info, |
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165 | ARRAY_SIZE(om5pac_mdio0_info)); |
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166 | |||
167 | ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00); |
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168 | ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01); |
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169 | |||
170 | /* GMAC0 is connected to the PHY1 */ |
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171 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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172 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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173 | ath79_eth0_data.phy_mask = BIT(1); |
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174 | ath79_eth0_pll_data.pll_1000 = 0x82000101; |
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175 | ath79_eth0_pll_data.pll_100 = 0x80000101; |
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176 | ath79_eth0_pll_data.pll_10 = 0x80001313; |
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177 | ath79_register_eth(0); |
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178 | |||
179 | /* GMAC1 is connected to MDIO1 in SGMII mode */ |
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180 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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181 | ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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182 | ath79_eth1_data.phy_mask = BIT(2); |
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183 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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184 | ath79_eth1_pll_data.pll_100 = 0x80000101; |
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185 | ath79_eth1_pll_data.pll_10 = 0x80001313; |
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186 | ath79_eth1_data.speed = SPEED_1000; |
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187 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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188 | ath79_register_eth(1); |
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189 | |||
190 | ath79_register_pci(); |
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191 | } |
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192 | |||
193 | MIPS_MACHINE(ATH79_MACH_OM5P_AC, "OM5P-AC", "OpenMesh OM5P AC", om5p_ac_setup); |