OpenWrt – Blame information for rev 3
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Qxwlan E558 v2 board support |
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3 | * |
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4 | * Copyright (C) 2017 Peng Zhang <sd20@qxwlan.com> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify it |
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7 | * under the terms of the GNU General Public License version 2 as published |
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8 | * by the Free Software Foundation. |
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9 | */ |
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10 | |||
11 | #include <linux/phy.h> |
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12 | #include <linux/gpio.h> |
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13 | #include <linux/platform_device.h> |
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14 | #include <linux/ath9k_platform.h> |
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15 | #include <linux/ar8216_platform.h> |
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16 | |||
17 | #include <asm/mach-ath79/ar71xx_regs.h> |
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18 | |||
19 | #include "common.h" |
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20 | #include "dev-ap9x-pci.h" |
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21 | #include "dev-eth.h" |
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22 | #include "dev-gpio-buttons.h" |
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23 | #include "dev-leds-gpio.h" |
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24 | #include "dev-m25p80.h" |
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25 | #include "dev-spi.h" |
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26 | #include "dev-usb.h" |
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27 | #include "dev-wmac.h" |
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28 | #include "machtypes.h" |
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29 | #include "pci.h" |
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30 | |||
31 | #define E558_V2_GPIO_LED_WLAN 13 |
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32 | #define E558_V2_GPIO_LED_SYSTEM 14 |
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33 | #define E558_V2_GPIO_LED_QSS 15 |
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34 | |||
35 | #define E558_V2_GPIO_BTN_RESET 16 |
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36 | |||
37 | #define E558_V2_KEYS_POLL_INTERVAL 20 /* msecs */ |
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38 | #define E558_V2_KEYS_DEBOUNCE_INTERVAL (3 * E558_V2_KEYS_POLL_INTERVAL) |
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39 | |||
40 | static struct gpio_led e558_v2_leds_gpio[] __initdata = { |
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41 | { |
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42 | .name = "e558-v2:green:qss", |
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43 | .gpio = E558_V2_GPIO_LED_QSS, |
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44 | .active_low = 1, |
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45 | }, |
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46 | { |
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47 | .name = "e558-v2:green:system", |
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48 | .gpio = E558_V2_GPIO_LED_SYSTEM, |
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49 | .active_low = 1, |
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50 | }, |
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51 | { |
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52 | .name = "e558-v2:green:wlan", |
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53 | .gpio = E558_V2_GPIO_LED_WLAN, |
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54 | .active_low = 1, |
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55 | }, |
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56 | }; |
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57 | |||
58 | static struct gpio_keys_button e558_v2_gpio_keys[] __initdata = { |
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59 | { |
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60 | .desc = "reset", |
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61 | .type = EV_KEY, |
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62 | .code = KEY_RESTART, |
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63 | .debounce_interval = E558_V2_KEYS_DEBOUNCE_INTERVAL, |
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64 | .gpio = E558_V2_GPIO_BTN_RESET, |
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65 | .active_low = 1, |
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66 | }, |
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67 | }; |
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68 | |||
69 | /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */ |
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70 | static struct ar8327_pad_cfg e558_v2_ar8327_pad0_cfg = { |
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71 | .mode = AR8327_PAD_MAC_SGMII, |
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72 | .sgmii_delay_en = true, |
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73 | }; |
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74 | |||
75 | /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */ |
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76 | static struct ar8327_pad_cfg e558_v2_ar8327_pad6_cfg = { |
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77 | .mode = AR8327_PAD_MAC_RGMII, |
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78 | .txclk_delay_en = true, |
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79 | .rxclk_delay_en = true, |
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80 | .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, |
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81 | .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, |
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82 | }; |
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83 | |||
84 | static const struct ar8327_led_info e558_v2_leds_qca8334[] = { |
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85 | AR8327_LED_INFO(PHY2_0, HW, "e558-v2:green:wan"), |
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86 | AR8327_LED_INFO(PHY3_0, HW, "e558-v2:green:lan1"), |
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87 | AR8327_LED_INFO(PHY4_0, HW, "e558-v2:green:lan2"), |
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88 | }; |
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89 | |||
90 | static struct ar8327_led_cfg e558_v2_ar8327_led_cfg = { |
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91 | .led_ctrl0 = 0xc737c737, |
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92 | .led_ctrl1 = 0x00000000, |
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93 | .led_ctrl2 = 0x00000000, |
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94 | .led_ctrl3 = 0x0030c300, |
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95 | .open_drain = false, |
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96 | }; |
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97 | |||
98 | static struct ar8327_platform_data e558_v2_ar8327_data = { |
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99 | .pad0_cfg = &e558_v2_ar8327_pad0_cfg, |
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100 | .pad6_cfg = &e558_v2_ar8327_pad6_cfg, |
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101 | .port0_cfg = { |
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102 | .force_link = 1, |
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103 | .speed = AR8327_PORT_SPEED_1000, |
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104 | .duplex = 1, |
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105 | .txpause = 1, |
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106 | .rxpause = 1, |
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107 | }, |
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108 | .port6_cfg = { |
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109 | .force_link = 1, |
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110 | .speed = AR8327_PORT_SPEED_1000, |
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111 | .duplex = 1, |
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112 | .txpause = 1, |
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113 | .rxpause = 1, |
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114 | }, |
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115 | .led_cfg = &e558_v2_ar8327_led_cfg, |
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116 | .leds = e558_v2_leds_qca8334, |
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117 | .num_leds = ARRAY_SIZE(e558_v2_leds_qca8334), |
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118 | }; |
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119 | |||
120 | static struct mdio_board_info e558_v2_mdio0_info[] = { |
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121 | { |
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122 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 123 | .phy_addr = 0, |
1 | office | 124 | .platform_data = &e558_v2_ar8327_data, |
125 | }, |
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126 | }; |
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127 | |||
128 | static void __init e558_v2_setup(void) |
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129 | { |
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130 | u8 *mac = (u8 *) KSEG1ADDR(0x1f050400); |
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131 | u8 *art = (u8 *) KSEG1ADDR(0x1f061000); |
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132 | |||
133 | ath79_register_m25p80(NULL); |
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134 | ath79_register_leds_gpio(-1, ARRAY_SIZE(e558_v2_leds_gpio), |
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135 | e558_v2_leds_gpio); |
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136 | |||
137 | ath79_register_gpio_keys_polled(-1, E558_V2_KEYS_POLL_INTERVAL, |
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138 | ARRAY_SIZE(e558_v2_gpio_keys), |
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139 | e558_v2_gpio_keys); |
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140 | |||
141 | ath79_register_mdio(0, 0x0); |
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142 | mdiobus_register_board_info(e558_v2_mdio0_info, |
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143 | ARRAY_SIZE(e558_v2_mdio0_info)); |
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144 | |||
145 | ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN); |
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146 | |||
147 | /* GMAC0 is connected to the RMGII interface */ |
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148 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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149 | ath79_eth0_data.phy_mask = BIT(0); |
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150 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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151 | ath79_eth0_pll_data.pll_1000 = 0x56000000; |
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152 | ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1); |
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153 | ath79_register_eth(0); |
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154 | |||
155 | /* GMAC1 is connected to the SGMII interface */ |
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156 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII; |
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157 | ath79_eth1_data.speed = SPEED_1000; |
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158 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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159 | ath79_eth1_pll_data.pll_1000 = 0x03000101; |
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160 | ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0); |
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161 | ath79_register_eth(1); |
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162 | |||
163 | ath79_register_pci(); |
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164 | ath79_register_usb(); |
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165 | ath79_register_wmac(art, NULL); |
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166 | } |
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167 | |||
168 | MIPS_MACHINE(ATH79_MACH_E558_V2, "E558-V2", "Qxwlan E558 v2", |
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169 | e558_v2_setup); |
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170 |