OpenWrt – Blame information for rev 3
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1 | office | 1 | /* |
2 | * Wallys DR342/DR344 boards support |
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3 | * |
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4 | * Copyright (c) 2011 Qualcomm Atheros |
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5 | * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org> |
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6 | * Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net> |
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7 | * Copyright (c) 2017 Piotr Dymacz <pepe2k@gmail.com> |
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8 | * |
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9 | * Permission to use, copy, modify, and/or distribute this software for any |
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10 | * purpose with or without fee is hereby granted, provided that the above |
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11 | * copyright notice and this permission notice appear in all copies. |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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14 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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15 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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16 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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17 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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18 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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19 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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20 | * |
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21 | */ |
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22 | |||
23 | #include <linux/gpio.h> |
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24 | #include <linux/phy.h> |
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25 | #include <linux/platform_device.h> |
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26 | #include <linux/ath9k_platform.h> |
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27 | #include <linux/platform_data/phy-at803x.h> |
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28 | |||
29 | #include <asm/mach-ath79/ar71xx_regs.h> |
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30 | |||
31 | #include "common.h" |
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32 | #include "pci.h" |
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33 | #include "dev-ap9x-pci.h" |
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34 | #include "dev-gpio-buttons.h" |
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35 | #include "dev-eth.h" |
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36 | #include "dev-usb.h" |
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37 | #include "dev-leds-gpio.h" |
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38 | #include "dev-m25p80.h" |
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39 | #include "dev-spi.h" |
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40 | #include "dev-wmac.h" |
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41 | #include "machtypes.h" |
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42 | |||
43 | #define DR34X_GPIO_LED_SIG1 12 |
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44 | #define DR34X_GPIO_LED_SIG2 13 |
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45 | #define DR34X_GPIO_LED_SIG3 14 |
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46 | #define DR34X_GPIO_LED_SIG4 15 |
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47 | #define DR34X_GPIO_LED_STATUS 11 |
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48 | #define DR344_GPIO_LED_LAN 17 |
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49 | #define DR344_GPIO_EXTERNAL_LNA0 18 |
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50 | #define DR344_GPIO_EXTERNAL_LNA1 19 |
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51 | |||
52 | #define DR34X_GPIO_BTN_RESET 16 |
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53 | |||
54 | #define DR344_KEYS_POLL_INTERVAL 20 /* msecs */ |
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55 | #define DR344_KEYS_DEBOUNCE_INTERVAL (3 * DR344_KEYS_POLL_INTERVAL) |
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56 | |||
57 | #define DR34X_MAC0_OFFSET 0 |
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58 | #define DR34X_MAC1_OFFSET 8 |
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59 | #define DR34X_WMAC_CALDATA_OFFSET 0x1000 |
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60 | |||
61 | static struct gpio_led dr342_leds_gpio[] __initdata = { |
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62 | { |
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63 | .name = "dr342:green:status", |
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64 | .gpio = DR34X_GPIO_LED_STATUS, |
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65 | .active_low = 1, |
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66 | }, |
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67 | { |
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68 | .name = "dr342:green:sig1", |
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69 | .gpio = DR34X_GPIO_LED_SIG1, |
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70 | .active_low = 1, |
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71 | }, |
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72 | { |
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73 | .name = "dr342:green:sig2", |
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74 | .gpio = DR34X_GPIO_LED_SIG2, |
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75 | .active_low = 1, |
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76 | }, |
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77 | { |
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78 | .name = "dr342:green:sig3", |
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79 | .gpio = DR34X_GPIO_LED_SIG3, |
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80 | .active_low = 1, |
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81 | }, |
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82 | { |
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83 | .name = "dr342:green:sig4", |
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84 | .gpio = DR34X_GPIO_LED_SIG4, |
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85 | .active_low = 1, |
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86 | } |
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87 | }; |
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88 | |||
89 | static struct gpio_led dr344_leds_gpio[] __initdata = { |
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90 | { |
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91 | .name = "dr344:green:lan", |
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92 | .gpio = DR344_GPIO_LED_LAN, |
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93 | .active_low = 1, |
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94 | }, |
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95 | { |
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96 | .name = "dr344:green:status", |
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97 | .gpio = DR34X_GPIO_LED_STATUS, |
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98 | .active_low = 1, |
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99 | }, |
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100 | { |
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101 | .name = "dr344:green:sig1", |
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102 | .gpio = DR34X_GPIO_LED_SIG1, |
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103 | .active_low = 1, |
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104 | }, |
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105 | { |
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106 | .name = "dr344:green:sig2", |
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107 | .gpio = DR34X_GPIO_LED_SIG2, |
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108 | .active_low = 1, |
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109 | }, |
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110 | { |
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111 | .name = "dr344:green:sig3", |
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112 | .gpio = DR34X_GPIO_LED_SIG3, |
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113 | .active_low = 1, |
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114 | }, |
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115 | { |
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116 | .name = "dr344:green:sig4", |
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117 | .gpio = DR34X_GPIO_LED_SIG4, |
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118 | .active_low = 1, |
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119 | } |
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120 | }; |
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121 | |||
122 | static struct gpio_keys_button dr34x_gpio_keys[] __initdata = { |
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123 | { |
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124 | .desc = "reset", |
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125 | .type = EV_KEY, |
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126 | .code = KEY_RESTART, |
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127 | .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL, |
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128 | .gpio = DR34X_GPIO_BTN_RESET, |
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129 | .active_low = 1, |
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130 | }, |
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131 | }; |
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132 | |||
133 | static struct at803x_platform_data dr34x_at803x_data = { |
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134 | .disable_smarteee = 1, |
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135 | .enable_rgmii_rx_delay = 1, |
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136 | .enable_rgmii_tx_delay = 1, |
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137 | }; |
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138 | |||
139 | static struct mdio_board_info dr34x_mdio0_info[] = { |
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140 | { |
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141 | .bus_id = "ag71xx-mdio.0", |
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3 | office | 142 | .phy_addr = 0, |
1 | office | 143 | .platform_data = &dr34x_at803x_data, |
144 | }, |
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145 | }; |
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146 | |||
147 | static void __init dr34x_setup(void) |
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148 | { |
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149 | u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); |
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150 | u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810); |
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151 | |||
152 | ath79_register_m25p80(NULL); |
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153 | |||
154 | ath79_gpio_direction_select(DR34X_GPIO_LED_STATUS, true); |
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155 | gpio_set_value(DR34X_GPIO_LED_STATUS, 1); |
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156 | ath79_gpio_output_select(DR34X_GPIO_LED_STATUS, 0); |
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157 | |||
158 | ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL, |
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159 | ARRAY_SIZE(dr34x_gpio_keys), |
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160 | dr34x_gpio_keys); |
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161 | |||
162 | ath79_register_usb(); |
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163 | |||
164 | ath79_register_wmac(art + DR34X_WMAC_CALDATA_OFFSET, NULL); |
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165 | |||
166 | ath79_register_pci(); |
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167 | |||
168 | mdiobus_register_board_info(dr34x_mdio0_info, |
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169 | ARRAY_SIZE(dr34x_mdio0_info)); |
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170 | |||
171 | ath79_register_mdio(0, 0x0); |
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172 | |||
173 | ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 | |
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174 | AR934X_ETH_CFG_SW_ONLY_MODE); |
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175 | |||
176 | /* GMAC0 is connected to an AR8035 Gbps PHY */ |
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177 | ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; |
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178 | ath79_eth0_data.phy_mask = BIT(0); |
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179 | ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev; |
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180 | ath79_eth0_pll_data.pll_1000 = 0x02000000; |
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181 | ath79_eth0_pll_data.pll_100 = 0x0101; |
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182 | ath79_eth0_pll_data.pll_10 = 0x1313; |
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183 | |||
184 | ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR34X_MAC0_OFFSET, 0); |
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185 | ath79_register_eth(0); |
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186 | } |
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187 | |||
188 | static void __init dr342_setup(void) |
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189 | { |
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190 | dr34x_setup(); |
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191 | |||
192 | ath79_register_leds_gpio(-1, ARRAY_SIZE(dr342_leds_gpio), |
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193 | dr342_leds_gpio); |
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194 | } |
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195 | |||
196 | static void __init dr344_setup(void) |
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197 | { |
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198 | u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810); |
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199 | |||
200 | dr34x_setup(); |
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201 | |||
202 | ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true); |
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203 | gpio_set_value(DR344_GPIO_LED_LAN, 1); |
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204 | ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0); |
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205 | |||
206 | ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio), |
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207 | dr344_leds_gpio); |
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208 | |||
209 | ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0); |
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210 | ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1); |
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211 | |||
212 | ath79_register_mdio(1, 0x0); |
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213 | |||
214 | /* GMAC1 is connected to the internal switch */ |
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215 | ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII; |
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216 | ath79_eth1_data.speed = SPEED_1000; |
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217 | ath79_eth1_data.duplex = DUPLEX_FULL; |
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218 | |||
219 | ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR34X_MAC1_OFFSET, 0); |
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220 | ath79_register_eth(1); |
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221 | } |
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222 | |||
223 | MIPS_MACHINE(ATH79_MACH_DR342, "DR342", "Wallys DR342", dr342_setup); |
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224 | MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup); |