OpenWrt – Blame information for rev 2

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1 office 1 /*
2 * PowerCloud Systems CR3000 support
3 *
4 * Copyright (c) 2011 Qualcomm Atheros
5 * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (c) 2012-2013 PowerCloud Systems
7 * Copyright (c) 2015 Daniel Dickinson <openwrt@daniel.thecshore.com>
8 *
9 * Permission to use, copy, modify, and/or distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22  
23 #include <linux/gpio.h>
24 #include <linux/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/ath9k_platform.h>
27 #include <linux/ar8216_platform.h>
28  
29 #include <asm/mach-ath79/ar71xx_regs.h>
30 #include <asm/mach-ath79/ath79.h>
31  
32 #include "common.h"
33 #include "dev-eth.h"
34 #include "dev-gpio-buttons.h"
35 #include "dev-leds-gpio.h"
36 #include "dev-m25p80.h"
37 #include "dev-spi.h"
38 #include "dev-wmac.h"
39 #include "machtypes.h"
40  
41 #define CR3000_GPIO_LED_WLAN_2G 13
42 #define CR3000_GPIO_LED_POWER_AMBER 15
43 #define CR3000_GPIO_LED_WAN 18
44 #define CR3000_GPIO_LED_LAN1 19
45 #define CR3000_GPIO_LED_LAN2 20
46 #define CR3000_GPIO_LED_LAN3 21
47 #define CR3000_GPIO_LED_LAN4 22
48  
49 #define CR3000_GPIO_BTN_WPS 16
50 #define CR3000_GPIO_BTN_RESET 17
51  
52 #define CR3000_KEYS_POLL_INTERVAL 20 /* msecs */
53 #define CR3000_KEYS_DEBOUNCE_INTERVAL (3 * CR3000_KEYS_POLL_INTERVAL)
54  
55 #define CR3000_MAC0_OFFSET 0
56 #define CR3000_MAC1_OFFSET 6
57 #define CR3000_WMAC_CALDATA_OFFSET 0x1000
58 #define CR3000_WMAC_MAC_OFFSET 0x1002
59  
60 static struct gpio_led cr3000_leds_gpio[] __initdata = {
61 {
62 .name = "pcs:amber:power",
63 .gpio = CR3000_GPIO_LED_POWER_AMBER,
64 .active_low = 1,
65 },
66 {
67 .name = "pcs:blue:wlan",
68 .gpio = CR3000_GPIO_LED_WLAN_2G,
69 .active_low = 1,
70 },
71 {
72 .name = "pcs:blue:wan",
73 .gpio = CR3000_GPIO_LED_WAN,
74 .active_low = 1,
75 },
76 {
77 .name = "pcs:blue:lan1",
78 .gpio = CR3000_GPIO_LED_LAN1,
79 .active_low = 1,
80 },
81 {
82 .name = "pcs:blue:lan2",
83 .gpio = CR3000_GPIO_LED_LAN2,
84 .active_low = 1,
85 },
86 {
87 .name = "pcs:blue:lan3",
88 .gpio = CR3000_GPIO_LED_LAN3,
89 .active_low = 1,
90 },
91 {
92 .name = "pcs:blue:lan4",
93 .gpio = CR3000_GPIO_LED_LAN4,
94 .active_low = 1,
95 },
96 };
97  
98 static struct gpio_keys_button cr3000_gpio_keys[] __initdata = {
99 {
100 .desc = "WPS button",
101 .type = EV_KEY,
102 .code = KEY_WPS_BUTTON,
103 .debounce_interval = CR3000_KEYS_DEBOUNCE_INTERVAL,
104 .gpio = CR3000_GPIO_BTN_WPS,
105 .active_low = 1,
106 },
107 {
108 .desc = "Reset button",
109 .type = EV_KEY,
110 .code = KEY_WPS_BUTTON,
111 .debounce_interval = CR3000_KEYS_DEBOUNCE_INTERVAL,
112 .gpio = CR3000_GPIO_BTN_RESET,
113 .active_low = 1,
114 },
115 };
116  
117 static void __init cr3000_setup(void)
118 {
119 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
120  
121 ath79_register_m25p80(NULL);
122  
123 ath79_register_leds_gpio(-1, ARRAY_SIZE(cr3000_leds_gpio),
124 cr3000_leds_gpio);
125  
126 ath79_register_gpio_keys_polled(-1, CR3000_KEYS_POLL_INTERVAL,
127 ARRAY_SIZE(cr3000_gpio_keys),
128 cr3000_gpio_keys);
129  
130 /* WLAN 2GHz onboard */
131 ath79_register_wmac(art + CR3000_WMAC_CALDATA_OFFSET, art + CR3000_WMAC_MAC_OFFSET);
132  
133 /* FE Lan on first 4-ports of internal switch and attached to GMAC1
134 * WAN Fast Ethernet interface attached to GMAC0
135 * Could be configured as a 5-port switch, but we use
136 * the SoC capabilities to attach port 5 to a separate PHY/MAC
137 * theoretically this leaves future possibility of using SoC
138 * acceleration/offloading.
139 */
140 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
141  
142 /* GMAC0 attached to PHY4 (port 5 of the internal switch) */
143 ath79_switch_data.phy4_mii_en = 1;
144 /* For switch carrier ignore port 5 (wan) */
145 ath79_switch_data.phy_poll_mask = 0x1;
146  
147 /* Register MII bus */
148 ath79_register_mdio(1, 0x0);
149  
150 /* GMAC0 attached to PHY4 (port 5 of the internal switch) */
151 ath79_switch_data.phy4_mii_en = 1;
152 ath79_switch_data.phy_poll_mask = 0x1;
153  
154 /* LAN */
155 ath79_init_mac(ath79_eth1_data.mac_addr, art + CR3000_MAC0_OFFSET, 0);
156 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
157 ath79_register_eth(1);
158  
159 /* Wan */
160 ath79_init_mac(ath79_eth0_data.mac_addr, art + CR3000_MAC0_OFFSET, 1);
161 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
162 ath79_eth0_data.phy_mask = BIT(0);
163 ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
164 ath79_register_eth(0);
165 }
166  
167 MIPS_MACHINE(ATH79_MACH_CR3000, "CR3000", "PowerCloud Systems CR3000",
168 cr3000_setup);