OpenWrt – Blame information for rev 1
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Rev | Author | Line No. | Line |
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1 | office | 1 | /* |
2 | * Device Tree for Bluestone (APM821xx) board. |
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3 | * |
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4 | * Copyright (c) 2010, Applied Micro Circuits Corporation |
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5 | * Author: Tirumala R Marri <tmarri@apm.com> |
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6 | * |
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7 | * This program is free software; you can redistribute it and/or |
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8 | * modify it under the terms of the GNU General Public License as |
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9 | * published by the Free Software Foundation; either version 2 of |
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10 | * the License, or (at your option) any later version. |
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11 | * |
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12 | * This program is distributed in the hope that it will be useful, |
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13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | * GNU General Public License for more details. |
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16 | * |
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17 | * You should have received a copy of the GNU General Public License |
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18 | * along with this program; if not, write to the Free Software |
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19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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20 | * MA 02111-1307 USA |
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21 | * |
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22 | */ |
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23 | |||
24 | #include <dt-bindings/dma/dw-dmac.h> |
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25 | #include <dt-bindings/input/input.h> |
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26 | #include <dt-bindings/interrupt-controller/irq.h> |
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27 | #include <dt-bindings/gpio/gpio.h> |
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28 | |||
29 | / { |
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30 | #address-cells = <2>; |
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31 | #size-cells = <1>; |
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32 | dcr-parent = <&{/cpus/cpu@0}>; |
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33 | compatible = "apm,bluestone"; |
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34 | |||
35 | aliases { |
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36 | ethernet0 = &EMAC0; /* needed for BSP u-boot */ |
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37 | }; |
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38 | |||
39 | cpus { |
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40 | #address-cells = <1>; |
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41 | #size-cells = <0>; |
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42 | |||
43 | CPU00: cpu@0 { |
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44 | device_type = "cpu"; |
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45 | model = "PowerPC,apm82181"; |
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46 | reg = <0x00000000>; |
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47 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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48 | timebase-frequency = <0>; /* Filled in by U-Boot */ |
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49 | i-cache-line-size = <32>; |
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50 | d-cache-line-size = <32>; |
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51 | i-cache-size = <32768>; |
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52 | d-cache-size = <32768>; |
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53 | dcr-controller; |
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54 | dcr-access-method = "native"; |
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55 | next-level-cache = <&L2C0>; |
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56 | }; |
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57 | }; |
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58 | |||
59 | memory { |
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60 | device_type = "memory"; |
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61 | reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ |
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62 | }; |
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63 | |||
64 | UIC0: interrupt-controller0 { |
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65 | compatible = "apm,uic-apm82181", "ibm,uic"; |
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66 | interrupt-controller; |
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67 | cell-index = <0>; |
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68 | dcr-reg = <0x0c0 0x009>; |
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69 | #address-cells = <0>; |
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70 | #size-cells = <0>; |
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71 | #interrupt-cells = <2>; |
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72 | }; |
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73 | |||
74 | UIC1: interrupt-controller1 { |
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75 | compatible = "apm,uic-apm82181", "ibm,uic"; |
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76 | interrupt-controller; |
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77 | cell-index = <1>; |
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78 | dcr-reg = <0x0d0 0x009>; |
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79 | #address-cells = <0>; |
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80 | #size-cells = <0>; |
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81 | #interrupt-cells = <2>; |
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82 | interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>, |
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83 | <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */ |
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84 | interrupt-parent = <&UIC0>; |
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85 | }; |
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86 | |||
87 | UIC2: interrupt-controller2 { |
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88 | compatible = "apm,uic-apm82181", "ibm,uic"; |
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89 | interrupt-controller; |
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90 | cell-index = <2>; |
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91 | dcr-reg = <0x0e0 0x009>; |
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92 | #address-cells = <0>; |
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93 | #size-cells = <0>; |
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94 | #interrupt-cells = <2>; |
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95 | interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>, |
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96 | <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */ |
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97 | interrupt-parent = <&UIC0>; |
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98 | }; |
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99 | |||
100 | UIC3: interrupt-controller3 { |
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101 | compatible = "apm,uic-apm82181","ibm,uic"; |
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102 | interrupt-controller; |
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103 | cell-index = <3>; |
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104 | dcr-reg = <0x0f0 0x009>; |
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105 | #address-cells = <0>; |
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106 | #size-cells = <0>; |
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107 | #interrupt-cells = <2>; |
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108 | interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>, |
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109 | <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */ |
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110 | interrupt-parent = <&UIC0>; |
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111 | }; |
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112 | |||
113 | OCM1: ocm@400040000 { |
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114 | compatible = "apm,ocm-apm82181", "ibm,ocm"; |
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115 | status = "okay"; |
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116 | cell-index = <1>; |
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117 | /* configured in U-Boot */ |
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118 | reg = <4 0x00040000 0x8000>; /* 32K */ |
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119 | }; |
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120 | |||
121 | SDR0: sdr { |
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122 | compatible = "apm,sdr-apm82181", "ibm,sdr-460ex"; |
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123 | dcr-reg = <0x00e 0x002>; |
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124 | }; |
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125 | |||
126 | CPR0: cpr { |
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127 | compatible = "apm,cpr-apm82181", "ibm,cpr-460ex"; |
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128 | dcr-reg = <0x00c 0x002>; |
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129 | }; |
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130 | |||
131 | L2C0: l2c { |
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132 | compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache"; |
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133 | dcr-reg = <0x020 0x008 |
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134 | 0x030 0x008>; |
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135 | cache-line-size = <32>; |
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136 | cache-size = <262144>; |
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137 | interrupt-parent = <&UIC1>; |
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138 | interrupts = <0x0b IRQ_TYPE_EDGE_RISING>; |
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139 | }; |
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140 | |||
141 | CPM0: cpm { |
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142 | compatible = "ibm,cpm-apm821xx", "ibm,cpm"; |
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143 | cell-index = <0>; |
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144 | dcr-reg = <0x160 0x003>; |
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145 | pm-cpu = <0x02000000>; |
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146 | pm-doze = <0x302570F0>; |
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147 | pm-nap = <0x302570F0>; |
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148 | pm-deepsleep = <0x302570F0>; |
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149 | pm-iic-device = <&IIC0>; |
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150 | pm-emac-device = <&EMAC0>; |
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151 | unused-units = <0x00000100>; |
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152 | idle-doze = <0x02000000>; |
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153 | standby = <0xfeff791d>; |
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154 | }; |
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155 | |||
156 | plb { |
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157 | compatible = "apm,plb-apm82181", "ibm,plb-460ex", "ibm,plb4"; |
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158 | #address-cells = <2>; |
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159 | #size-cells = <1>; |
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160 | ranges; /* Filled in by U-Boot */ |
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161 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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162 | |||
163 | SDRAM0: sdram { |
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164 | compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp"; |
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165 | dcr-reg = <0x010 0x002>; |
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166 | }; |
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167 | |||
168 | RTC: rtc { |
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169 | compatible = "ibm,rtc"; |
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170 | dcr-reg = <0x240 0x009>; |
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171 | interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>; |
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172 | interrupt-parent = <&UIC2>; |
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173 | |||
174 | }; |
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175 | |||
176 | TRNG: trng@110000 { |
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177 | compatible = "amcc,ppc460ex-rng", "ppc4xx-rng", "amcc, ppc4xx-trng"; |
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178 | reg = <4 0x00110000 0x100>; |
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179 | interrupt-parent = <&UIC1>; |
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180 | interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>; |
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181 | status = "disabled"; |
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182 | }; |
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183 | |||
184 | PKA: pka@114000 { |
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185 | compatible = "ppc4xx-pka", "amcc,ppc4xx-pka", "amcc, ppc4xx-pka"; |
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186 | reg = <4 0x00114000 0x4000>; |
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187 | interrupt-parent = <&UIC0>; |
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188 | interrupts = <0x14 IRQ_TYPE_EDGE_RISING>; |
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189 | status = "disabled"; |
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190 | }; |
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191 | |||
192 | CRYPTO: crypto@180000 { |
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193 | compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto"; |
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194 | reg = <4 0x00180000 0x80400>; |
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195 | interrupt-parent = <&UIC0>; |
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196 | interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>; |
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197 | status = "disabled"; /* hardware option */ |
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198 | }; |
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199 | |||
200 | MAL0: mcmal { |
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201 | compatible = "ibm,mcmal-460ex", "ibm,mcmal2"; |
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202 | descriptor-memory = "ocm"; |
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203 | dcr-reg = <0x180 0x062>; |
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204 | num-tx-chans = <1>; |
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205 | num-rx-chans = <1>; |
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206 | #address-cells = <0>; |
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207 | #size-cells = <0>; |
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208 | interrupt-parent = <&UIC2>; |
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209 | interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>, |
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210 | <0x07 IRQ_TYPE_LEVEL_HIGH>, |
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211 | <0x03 IRQ_TYPE_LEVEL_HIGH>, |
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212 | <0x04 IRQ_TYPE_LEVEL_HIGH>, |
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213 | <0x05 IRQ_TYPE_LEVEL_HIGH>, |
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214 | <0x08 IRQ_TYPE_EDGE_FALLING>, |
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215 | <0x09 IRQ_TYPE_EDGE_FALLING>, |
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216 | <0x0c IRQ_TYPE_EDGE_FALLING>, |
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217 | <0x0d IRQ_TYPE_EDGE_FALLING>; |
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218 | interrupt-names = "txeob", "rxeob", "serr", |
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219 | "txde", "rxde", |
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220 | "tx0coal", "tx1coal", |
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221 | "rx0coal", "rx1coal"; |
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222 | }; |
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223 | |||
224 | POB0: opb { |
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225 | compatible = "ibm,opb-460ex", "ibm,opb"; |
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226 | #address-cells = <1>; |
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227 | #size-cells = <1>; |
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228 | ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; |
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229 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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230 | |||
231 | EBC0: ebc { |
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232 | compatible = "ibm,ebc-460ex", "ibm,ebc"; |
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233 | dcr-reg = <0x012 0x002>; |
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234 | #address-cells = <2>; |
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235 | #size-cells = <1>; |
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236 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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237 | /* ranges property is supplied by U-Boot */ |
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238 | ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>; |
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239 | interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>; |
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240 | interrupt-parent = <&UIC1>; |
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241 | |||
242 | nor_flash@0,0 { |
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243 | compatible = "cfi-flash"; |
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244 | bank-width = <1>; |
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245 | reg = <0x00000000 0x00000000 0x00100000>; |
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246 | #address-cells = <1>; |
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247 | #size-cells = <1>; |
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248 | status = "disabled"; |
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249 | }; |
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250 | |||
251 | ndfc@1,0 { |
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252 | compatible = "ibm,ndfc"; |
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253 | reg = <00000003 00000000 00002000>; |
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254 | ccr = <0x00001000>; |
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255 | bank-settings = <0x80002222>; |
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256 | status = "disabled"; |
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257 | |||
258 | nand { |
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259 | #address-cells = <1>; |
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260 | #size-cells = <1>; |
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261 | }; |
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262 | }; |
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263 | }; |
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264 | |||
265 | UART0: serial@ef600300 { |
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266 | /* |
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267 | * AMCC's BSP u-boot scans for the "ns16550" |
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268 | * compatible, without it, u-boot wouldn't |
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269 | * set the required "clock-frequency". |
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270 | * |
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271 | * The hardware documentation states: |
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272 | * "Register compatibility with 16750 register set" |
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273 | */ |
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274 | compatible = "ns16750", "ns16550"; |
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275 | reg = <0xef600300 0x00000008>; |
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276 | virtual-reg = <0xef600300>; |
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277 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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278 | interrupt-parent = <&UIC1>; |
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279 | interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>; |
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280 | status = "disabled"; |
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281 | }; |
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282 | |||
283 | UART1: serial@ef600400 { |
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284 | /* same "ns16750" as with UART0 */ |
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285 | compatible = "ns16750", "ns16550"; |
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286 | reg = <0xef600400 0x00000008>; |
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287 | virtual-reg = <0xef600400>; |
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288 | clock-frequency = <0>; /* Filled in by U-Boot */ |
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289 | interrupt-parent = <&UIC0>; |
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290 | interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>; |
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291 | status = "disabled"; |
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292 | }; |
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293 | |||
294 | IIC0: i2c@ef600700 { |
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295 | compatible = "ibm,iic-460ex", "ibm,iic"; |
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296 | reg = <0xef600700 0x00000014>; |
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297 | interrupt-parent = <&UIC0>; |
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298 | interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>; |
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299 | #address-cells = <1>; |
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300 | #size-cells = <0>; |
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301 | status = "disabled"; |
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302 | }; |
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303 | |||
304 | IIC1: i2c@ef600800 { |
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305 | compatible = "ibm,iic-460ex", "ibm,iic"; |
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306 | reg = <0xef600800 0x00000014>; |
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307 | interrupt-parent = <&UIC0>; |
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308 | interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>; |
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309 | status = "disabled"; |
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310 | }; |
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311 | |||
312 | GPIO0: gpio@ef600b00 { |
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313 | compatible = "ibm,ppc4xx-gpio"; |
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314 | reg = <0xef600b00 0x00000048>; |
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315 | #gpio-cells = <2>; |
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316 | gpio-controller; |
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317 | status = "disabled"; |
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318 | }; |
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319 | |||
320 | EMAC0: ethernet@ef600c00 { |
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321 | device_type = "network"; |
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322 | compatible = "ibm,emac-apm821xx", "ibm,emac4sync"; |
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323 | interrupt-parent = <&EMAC0>; |
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324 | interrupts = <0 1>; |
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325 | #interrupt-cells = <1>; |
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326 | #address-cells = <0>; |
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327 | #size-cells = <0>; |
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328 | interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>, |
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329 | <1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>; |
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330 | interrupt-names = "status", "wake"; |
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331 | |||
332 | reg = <0xef600c00 0x000000c4>; |
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333 | local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
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334 | mal-device = <&MAL0>; |
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335 | mal-tx-channel = <0>; |
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336 | mal-rx-channel = <0>; |
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337 | cell-index = <0>; |
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338 | max-frame-size = <9000>; |
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339 | rx-fifo-size = <16384>; |
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340 | tx-fifo-size = <2048>; |
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341 | phy-mode = "rgmii"; |
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342 | phy-map = <0x00000000>; |
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343 | rgmii-device = <&RGMII0>; |
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344 | rgmii-channel = <0>; |
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345 | tah-device = <&TAH0>; |
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346 | tah-channel = <0>; |
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347 | has-inverted-stacr-oc; |
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348 | has-new-stacr-staopc; |
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349 | status = "disabled"; |
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350 | }; |
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351 | |||
352 | TAH0: emac-tah@ef601350 { |
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353 | compatible = "ibm,tah-460ex", "ibm,tah"; |
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354 | reg = <0xef601350 0x00000030>; |
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355 | }; |
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356 | |||
357 | RGMII0: emac-rgmii@ef601500 { |
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358 | compatible = "ibm,rgmii-405ex", "ibm,rgmii"; |
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359 | reg = <0xef601500 0x00000008>; |
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360 | has-mdio; |
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361 | }; |
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362 | }; |
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363 | |||
364 | USBOTG0: usbotg@bff80000 { |
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365 | compatible = "amcc,dwc-otg"; |
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366 | reg = <4 0xbff80000 0x10000>; |
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367 | interrupt-parent = <&USBOTG0>; |
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368 | interrupts = <0 1 2>; |
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369 | #interrupt-cells = <1>; |
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370 | #address-cells = <0>; |
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371 | #size-cells = <0>; |
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372 | interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>, |
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373 | <1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>, |
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374 | <2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>; |
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375 | interrupt-names = "usb-otg", "high-power", "dma"; |
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376 | dr_mode = "host"; |
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377 | status = "disabled"; |
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378 | }; |
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379 | |||
380 | AHBDMA0: dma@bffd0800 { |
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381 | compatible = "snps,dma-spear1340"; |
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382 | reg = <4 0xbffd0800 0x400>; |
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383 | interrupt-parent = <&UIC0>; |
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384 | interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>; |
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385 | #dma-cells = <3>; |
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386 | |||
387 | dma-channels = <2>; |
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388 | dma-masters = <3>; |
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389 | block_size = <4095>; |
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390 | data-width = <4>, <4>, <4>; |
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391 | multi-block = <1>, <1>; |
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392 | |||
393 | chan_allocation_order = <1>; |
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394 | chan_priority = <1>; |
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395 | |||
396 | snps,dma-protection-control = |
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397 | <(DW_DMAC_HPROT1_PRIVILEGED_MODE | |
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398 | DW_DMAC_HPROT2_BUFFERABLE)>; |
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399 | is_memcpy; |
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400 | }; |
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401 | |||
402 | SATA0: sata@bffd1000 { |
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403 | compatible = "amcc,sata-460ex"; |
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404 | reg = <4 0xbffd1000 0x800>; |
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405 | interrupt-parent = <&UIC0>; |
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406 | interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>; |
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407 | dmas = <&AHBDMA0 0 0 1>; |
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408 | dma-names = "sata-dma"; |
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409 | status = "disabled"; |
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410 | }; |
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411 | |||
412 | SATA1: sata@bffd1800 { |
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413 | compatible = "amcc,sata-460ex"; |
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414 | reg = <4 0xbffd1800 0x800>; |
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415 | interrupt-parent = <&UIC0>; |
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416 | interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>; |
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417 | dmas = <&AHBDMA0 1 0 2>; |
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418 | dma-names = "sata-dma"; |
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419 | status = "disabled"; |
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420 | }; |
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421 | |||
422 | MSI: ppc4xx-msi@c10000000 { |
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423 | compatible = "amcc,ppc4xx-msi", "ppc4xx-msi"; |
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424 | reg = <0xc 0x10000000 0x100 |
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425 | 0xc 0x10000000 0x100>; |
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426 | sdr-base = <0x36C>; |
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427 | msi-data = <0x00004440>; |
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428 | msi-mask = <0x0000ffe0>; |
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429 | interrupts =<0 1 2 3 4 5 6 7>; |
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430 | interrupt-parent = <&MSI>; |
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431 | #interrupt-cells = <1>; |
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432 | #address-cells = <0>; |
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433 | #size-cells = <0>; |
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434 | msi-available-ranges = <0x0 0x100>; |
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435 | interrupt-map = |
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436 | <0 &UIC3 0x18 IRQ_TYPE_EDGE_RISING>, |
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437 | <1 &UIC3 0x19 IRQ_TYPE_EDGE_RISING>, |
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438 | <2 &UIC3 0x1a IRQ_TYPE_EDGE_RISING>, |
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439 | <3 &UIC3 0x1b IRQ_TYPE_EDGE_RISING>, |
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440 | <4 &UIC3 0x1c IRQ_TYPE_EDGE_RISING>, |
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441 | <5 &UIC3 0x1d IRQ_TYPE_EDGE_RISING>, |
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442 | <6 &UIC3 0x1e IRQ_TYPE_EDGE_RISING>, |
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443 | <7 &UIC3 0x1f IRQ_TYPE_EDGE_RISING>; |
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444 | status = "disabled"; |
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445 | }; |
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446 | |||
447 | PCIE0: pciex@d00000000 { |
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448 | device_type = "pci"; /* see ppc4xx_pci_find_bridge */ |
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449 | #interrupt-cells = <1>; |
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450 | #size-cells = <2>; |
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451 | #address-cells = <3>; |
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452 | compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex"; |
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453 | primary; |
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454 | port = <0x0>; /* port number */ |
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455 | reg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */ |
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456 | <0x0000000c 0x08010000 0x00001000>; /* Registers */ |
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457 | dcr-reg = <0x100 0x020>; |
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458 | sdr-base = <0x300>; |
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459 | |||
460 | /* Outbound ranges, one memory and one IO, |
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461 | * later cannot be changed |
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462 | */ |
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463 | ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>, |
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464 | <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>, |
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465 | <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; |
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466 | |||
467 | /* Inbound 2GB range starting at 0 */ |
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468 | dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
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469 | |||
470 | /* This drives busses 0x40 to 0x7f */ |
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471 | bus-range = <0x40 0x7f>; |
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472 | |||
473 | /* Legacy interrupts (note the weird polarity, the bridge seems |
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474 | * to invert PCIe legacy interrupts). |
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475 | * We are de-swizzling here because the numbers are actually for |
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476 | * port of the root complex virtual P2P bridge. But I want |
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477 | * to avoid putting a node for it in the tree, so the numbers |
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478 | * below are basically de-swizzled numbers. |
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479 | * The real slot is on idsel 0, so the swizzling is 1:1 |
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480 | */ |
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481 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
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482 | interrupt-map = |
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483 | <0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */ |
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484 | <0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */ |
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485 | <0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */ |
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486 | <0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */ |
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487 | status = "disabled"; |
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488 | }; |
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489 | }; |
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490 | }; |