OpenWrt – Blame information for rev 1

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Rev Author Line No. Line
1 office 1 --- a/drivers/tty/serial/amba-pl010.c
2 +++ b/drivers/tty/serial/amba-pl010.c
3 @@ -48,11 +48,10 @@
4 #include <linux/slab.h>
5 #include <linux/io.h>
6  
7 -#define UART_NR 8
8 -
9 #define SERIAL_AMBA_MAJOR 204
10 #define SERIAL_AMBA_MINOR 16
11 -#define SERIAL_AMBA_NR UART_NR
12 +#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
13 +#define SERIAL_AMBA_NAME CONFIG_SERIAL_AMBA_PL010_PORTNAME
14  
15 #define AMBA_ISR_PASS_LIMIT 256
16  
17 @@ -78,9 +77,9 @@ static void pl010_stop_tx(struct uart_po
18 struct uart_amba_port *uap = (struct uart_amba_port *)port;
19 unsigned int cr;
20  
21 - cr = readb(uap->port.membase + UART010_CR);
22 + cr = __raw_readl(uap->port.membase + UART010_CR);
23 cr &= ~UART010_CR_TIE;
24 - writel(cr, uap->port.membase + UART010_CR);
25 + __raw_writel(cr, uap->port.membase + UART010_CR);
26 }
27  
28 static void pl010_start_tx(struct uart_port *port)
29 @@ -88,9 +87,9 @@ static void pl010_start_tx(struct uart_p
30 struct uart_amba_port *uap = (struct uart_amba_port *)port;
31 unsigned int cr;
32  
33 - cr = readb(uap->port.membase + UART010_CR);
34 + cr = __raw_readl(uap->port.membase + UART010_CR);
35 cr |= UART010_CR_TIE;
36 - writel(cr, uap->port.membase + UART010_CR);
37 + __raw_writel(cr, uap->port.membase + UART010_CR);
38 }
39  
40 static void pl010_stop_rx(struct uart_port *port)
41 @@ -98,9 +97,9 @@ static void pl010_stop_rx(struct uart_po
42 struct uart_amba_port *uap = (struct uart_amba_port *)port;
43 unsigned int cr;
44  
45 - cr = readb(uap->port.membase + UART010_CR);
46 + cr = __raw_readl(uap->port.membase + UART010_CR);
47 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
48 - writel(cr, uap->port.membase + UART010_CR);
49 + __raw_writel(cr, uap->port.membase + UART010_CR);
50 }
51  
52 static void pl010_enable_ms(struct uart_port *port)
53 @@ -108,18 +107,18 @@ static void pl010_enable_ms(struct uart_
54 struct uart_amba_port *uap = (struct uart_amba_port *)port;
55 unsigned int cr;
56  
57 - cr = readb(uap->port.membase + UART010_CR);
58 + cr = __raw_readl(uap->port.membase + UART010_CR);
59 cr |= UART010_CR_MSIE;
60 - writel(cr, uap->port.membase + UART010_CR);
61 + __raw_writel(cr, uap->port.membase + UART010_CR);
62 }
63  
64 static void pl010_rx_chars(struct uart_amba_port *uap)
65 {
66 unsigned int status, ch, flag, rsr, max_count = 256;
67  
68 - status = readb(uap->port.membase + UART01x_FR);
69 + status = __raw_readl(uap->port.membase + UART01x_FR);
70 while (UART_RX_DATA(status) && max_count--) {
71 - ch = readb(uap->port.membase + UART01x_DR);
72 + ch = __raw_readl(uap->port.membase + UART01x_DR);
73 flag = TTY_NORMAL;
74  
75 uap->port.icount.rx++;
76 @@ -128,9 +127,9 @@ static void pl010_rx_chars(struct uart_a
77 * Note that the error handling code is
78 * out of the main execution path
79 */
80 - rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
81 + rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
82 if (unlikely(rsr & UART01x_RSR_ANY)) {
83 - writel(0, uap->port.membase + UART01x_ECR);
84 + __raw_writel(0, uap->port.membase + UART01x_ECR);
85  
86 if (rsr & UART01x_RSR_BE) {
87 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
88 @@ -160,7 +159,7 @@ static void pl010_rx_chars(struct uart_a
89 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
90  
91 ignore_char:
92 - status = readb(uap->port.membase + UART01x_FR);
93 + status = __raw_readl(uap->port.membase + UART01x_FR);
94 }
95 spin_unlock(&uap->port.lock);
96 tty_flip_buffer_push(&uap->port.state->port);
97 @@ -173,7 +172,7 @@ static void pl010_tx_chars(struct uart_a
98 int count;
99  
100 if (uap->port.x_char) {
101 - writel(uap->port.x_char, uap->port.membase + UART01x_DR);
102 + __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
103 uap->port.icount.tx++;
104 uap->port.x_char = 0;
105 return;
106 @@ -185,7 +184,7 @@ static void pl010_tx_chars(struct uart_a
107  
108 count = uap->port.fifosize >> 1;
109 do {
110 - writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
111 + __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
112 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
113 uap->port.icount.tx++;
114 if (uart_circ_empty(xmit))
115 @@ -203,9 +202,9 @@ static void pl010_modem_status(struct ua
116 {
117 unsigned int status, delta;
118  
119 - writel(0, uap->port.membase + UART010_ICR);
120 + __raw_writel(0, uap->port.membase + UART010_ICR);
121  
122 - status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
123 + status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
124  
125 delta = status ^ uap->old_status;
126 uap->old_status = status;
127 @@ -233,7 +232,7 @@ static irqreturn_t pl010_int(int irq, vo
128  
129 spin_lock(&uap->port.lock);
130  
131 - status = readb(uap->port.membase + UART010_IIR);
132 + status = __raw_readl(uap->port.membase + UART010_IIR);
133 if (status) {
134 do {
135 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
136 @@ -246,7 +245,7 @@ static irqreturn_t pl010_int(int irq, vo
137 if (pass_counter-- == 0)
138 break;
139  
140 - status = readb(uap->port.membase + UART010_IIR);
141 + status = __raw_readl(uap->port.membase + UART010_IIR);
142 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
143 UART010_IIR_TIS));
144 handled = 1;
145 @@ -260,7 +259,7 @@ static irqreturn_t pl010_int(int irq, vo
146 static unsigned int pl010_tx_empty(struct uart_port *port)
147 {
148 struct uart_amba_port *uap = (struct uart_amba_port *)port;
149 - unsigned int status = readb(uap->port.membase + UART01x_FR);
150 + unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
151 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
152 }
153  
154 @@ -270,7 +269,7 @@ static unsigned int pl010_get_mctrl(stru
155 unsigned int result = 0;
156 unsigned int status;
157  
158 - status = readb(uap->port.membase + UART01x_FR);
159 + status = __raw_readl(uap->port.membase + UART01x_FR);
160 if (status & UART01x_FR_DCD)
161 result |= TIOCM_CAR;
162 if (status & UART01x_FR_DSR)
163 @@ -296,12 +295,12 @@ static void pl010_break_ctl(struct uart_
164 unsigned int lcr_h;
165  
166 spin_lock_irqsave(&uap->port.lock, flags);
167 - lcr_h = readb(uap->port.membase + UART010_LCRH);
168 + lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
169 if (break_state == -1)
170 lcr_h |= UART01x_LCRH_BRK;
171 else
172 lcr_h &= ~UART01x_LCRH_BRK;
173 - writel(lcr_h, uap->port.membase + UART010_LCRH);
174 + __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
175 spin_unlock_irqrestore(&uap->port.lock, flags);
176 }
177  
178 @@ -329,12 +328,12 @@ static int pl010_startup(struct uart_por
179 /*
180 * initialise the old status of the modem signals
181 */
182 - uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
183 + uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
184  
185 /*
186 * Finally, enable interrupts
187 */
188 - writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
189 + __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
190 uap->port.membase + UART010_CR);
191  
192 return 0;
193 @@ -357,10 +356,10 @@ static void pl010_shutdown(struct uart_p
194 /*
195 * disable all interrupts, disable the port
196 */
197 - writel(0, uap->port.membase + UART010_CR);
198 + __raw_writel(0, uap->port.membase + UART010_CR);
199  
200 /* disable break condition and fifos */
201 - writel(readb(uap->port.membase + UART010_LCRH) &
202 + __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
203 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
204 uap->port.membase + UART010_LCRH);
205  
206 @@ -382,7 +381,7 @@ pl010_set_termios(struct uart_port *port
207 /*
208 * Ask the core to calculate the divisor for us.
209 */
210 - baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
211 + baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
212 quot = uart_get_divisor(port, baud);
213  
214 switch (termios->c_cflag & CSIZE) {
215 @@ -445,25 +444,25 @@ pl010_set_termios(struct uart_port *port
216 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
217  
218 /* first, disable everything */
219 - old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
220 + old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
221  
222 if (UART_ENABLE_MS(port, termios->c_cflag))
223 old_cr |= UART010_CR_MSIE;
224  
225 - writel(0, uap->port.membase + UART010_CR);
226 + __raw_writel(0, uap->port.membase + UART010_CR);
227  
228 /* Set baud rate */
229 quot -= 1;
230 - writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
231 - writel(quot & 0xff, uap->port.membase + UART010_LCRL);
232 + __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
233 + __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
234  
235 /*
236 * ----------v----------v----------v----------v-----
237 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
238 * ----------^----------^----------^----------^-----
239 */
240 - writel(lcr_h, uap->port.membase + UART010_LCRH);
241 - writel(old_cr, uap->port.membase + UART010_CR);
242 + __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
243 + __raw_writel(old_cr, uap->port.membase + UART010_CR);
244  
245 spin_unlock_irqrestore(&uap->port.lock, flags);
246 }
247 @@ -545,7 +544,7 @@ static struct uart_ops amba_pl010_pops =
248 .verify_port = pl010_verify_port,
249 };
250  
251 -static struct uart_amba_port *amba_ports[UART_NR];
252 +static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
253  
254 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
255  
256 @@ -555,10 +554,10 @@ static void pl010_console_putchar(struct
257 unsigned int status;
258  
259 do {
260 - status = readb(uap->port.membase + UART01x_FR);
261 + status = __raw_readl(uap->port.membase + UART01x_FR);
262 barrier();
263 } while (!UART_TX_READY(status));
264 - writel(ch, uap->port.membase + UART01x_DR);
265 + __raw_writel(ch, uap->port.membase + UART01x_DR);
266 }
267  
268 static void
269 @@ -572,8 +571,8 @@ pl010_console_write(struct console *co,
270 /*
271 * First save the CR then disable the interrupts
272 */
273 - old_cr = readb(uap->port.membase + UART010_CR);
274 - writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
275 + old_cr = __raw_readl(uap->port.membase + UART010_CR);
276 + __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
277  
278 uart_console_write(&uap->port, s, count, pl010_console_putchar);
279  
280 @@ -582,10 +581,10 @@ pl010_console_write(struct console *co,
281 * and restore the TCR
282 */
283 do {
284 - status = readb(uap->port.membase + UART01x_FR);
285 + status = __raw_readl(uap->port.membase + UART01x_FR);
286 barrier();
287 } while (status & UART01x_FR_BUSY);
288 - writel(old_cr, uap->port.membase + UART010_CR);
289 + __raw_writel(old_cr, uap->port.membase + UART010_CR);
290  
291 clk_disable(uap->clk);
292 }
293 @@ -594,9 +593,9 @@ static void __init
294 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
295 int *parity, int *bits)
296 {
297 - if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
298 + if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
299 unsigned int lcr_h, quot;
300 - lcr_h = readb(uap->port.membase + UART010_LCRH);
301 + lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
302  
303 *parity = 'n';
304 if (lcr_h & UART01x_LCRH_PEN) {
305 @@ -611,8 +610,8 @@ pl010_console_get_options(struct uart_am
306 else
307 *bits = 8;
308  
309 - quot = readb(uap->port.membase + UART010_LCRL) |
310 - readb(uap->port.membase + UART010_LCRM) << 8;
311 + quot = __raw_readl(uap->port.membase + UART010_LCRL) |
312 + __raw_readl(uap->port.membase + UART010_LCRM) << 8;
313 *baud = uap->port.uartclk / (16 * (quot + 1));
314 }
315 }
316 @@ -631,7 +630,7 @@ static int __init pl010_console_setup(st
317 * if so, search for the first available port that does have
318 * console support.
319 */
320 - if (co->index >= UART_NR)
321 + if (co->index >= SERIAL_AMBA_NR)
322 co->index = 0;
323 uap = amba_ports[co->index];
324 if (!uap)
325 @@ -653,7 +652,7 @@ static int __init pl010_console_setup(st
326  
327 static struct uart_driver amba_reg;
328 static struct console amba_console = {
329 - .name = "ttyAM",
330 + .name = SERIAL_AMBA_NAME,
331 .write = pl010_console_write,
332 .device = uart_console_device,
333 .setup = pl010_console_setup,
334 @@ -669,11 +668,11 @@ static struct console amba_console = {
335  
336 static struct uart_driver amba_reg = {
337 .owner = THIS_MODULE,
338 - .driver_name = "ttyAM",
339 - .dev_name = "ttyAM",
340 + .driver_name = SERIAL_AMBA_NAME,
341 + .dev_name = SERIAL_AMBA_NAME,
342 .major = SERIAL_AMBA_MAJOR,
343 .minor = SERIAL_AMBA_MINOR,
344 - .nr = UART_NR,
345 + .nr = SERIAL_AMBA_NR,
346 .cons = AMBA_CONSOLE,
347 };
348  
349 --- a/drivers/tty/serial/Kconfig
350 +++ b/drivers/tty/serial/Kconfig
351 @@ -25,10 +25,25 @@ config SERIAL_AMBA_PL010
352 help
353 This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
354 an Integrator/AP or Integrator/PP2 platform, or if you have a
355 - Cirrus Logic EP93xx CPU, say Y or M here.
356 + Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
357  
358 If unsure, say N.
359  
360 +config SERIAL_AMBA_PL010_NUMPORTS
361 + int "Maximum number of AMBA PL010 serial ports"
362 + depends on SERIAL_AMBA_PL010
363 + default "8"
364 + ---help---
365 + Set this to the number of serial ports you want the AMBA PL010 driver
366 + to support.
367 +
368 +config SERIAL_AMBA_PL010_PORTNAME
369 + string "Name of the AMBA PL010 serial ports"
370 + depends on SERIAL_AMBA_PL010
371 + default "ttyAM"
372 + ---help---
373 + ::: To be written :::
374 +
375 config SERIAL_AMBA_PL010_CONSOLE
376 bool "Support for console on AMBA serial port"
377 depends on SERIAL_AMBA_PL010=y