OpenWrt – Blame information for rev 2
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1 | office | 1 | /************************************************************************ |
2 | * |
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3 | * Copyright (c) 2005 |
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4 | * Infineon Technologies AG |
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5 | * St. Martin Strasse 53; 81669 Muenchen; Germany |
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6 | * |
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7 | ************************************************************************/ |
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8 | |||
9 | #ifndef __ADM8668_H__ |
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10 | #define __ADM8668_H__ |
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11 | |||
12 | /*======================= Physical Memory Map ============================*/ |
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13 | #define ADM8668_SDRAM_BASE 0 |
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14 | #define ADM8668_SMEM1_BASE 0x10000000 |
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15 | #define ADM8668_MPMC_BASE 0x11000000 |
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16 | #define ADM8668_USB_BASE 0x11200000 |
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17 | #define ADM8668_CONFIG_BASE 0x11400000 |
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18 | #define ADM8668_WAN_BASE 0x11600000 |
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19 | #define ADM8668_WLAN_BASE 0x11800000 |
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20 | #define ADM8668_LAN_BASE 0x11A00000 |
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21 | #define ADM8668_INTC_BASE 0x1E000000 |
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22 | #define ADM8668_TMR_BASE 0x1E200000 |
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23 | #define ADM8668_UART0_BASE 0x1E400000 |
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24 | #define ADM8668_SMEM0_BASE 0x1FC00000 |
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25 | #define ADM8668_NAND_BASE 0x1FFFFF00 |
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26 | |||
27 | #define ADM8668_PCICFG_BASE 0x12200000 |
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28 | #define ADM8668_PCIDAT_BASE 0x12400000 |
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29 | |||
30 | /* interrupt levels */ |
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31 | #define ADM8668_SWI_IRQ 1 |
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32 | #define ADM8668_COMMS_RX_IRQ 2 |
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33 | #define ADM8668_COMMS_TX_IRQ 3 |
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34 | #define ADM8668_TIMER0_IRQ 4 |
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35 | #define ADM8668_TIMER1_IRQ 5 |
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36 | #define ADM8668_UART0_IRQ 6 |
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37 | #define ADM8668_LAN_IRQ 7 |
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38 | #define ADM8668_WAN_IRQ 8 |
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39 | #define ADM8668_WLAN_IRQ 9 |
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40 | #define ADM8668_GPIO_IRQ 10 |
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41 | #define ADM8668_IDE_IRQ 11 |
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42 | #define ADM8668_PCI2_IRQ 12 |
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43 | #define ADM8668_PCI1_IRQ 13 |
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44 | #define ADM8668_PCI0_IRQ 14 |
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45 | #define ADM8668_USB_IRQ 15 |
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46 | #define ADM8668_IRQ_MAX ADM8668_USB_IRQ |
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47 | |||
48 | /* register access macros */ |
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49 | #define ADM8668_CONFIG_REG(_reg) \ |
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50 | (*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg))))) |
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51 | |||
52 | /* lan registers */ |
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53 | #define NETCSR6 0x30 |
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54 | #define NETCSR7 0x38 |
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55 | #define NETCSR37 0xF8 |
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56 | |||
57 | /* known/used CPU configuration registers */ |
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58 | #define ADM8668_CR0 0x00 |
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59 | #define ADM8668_CR1 0x04 |
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60 | #define ADM8668_CR3 0x0C |
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61 | #define ADM8668_CR66 0x108 |
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62 | |||
63 | /** For GPIO control **/ |
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64 | #define GPIO_REG 0x5C /* on WLAN */ |
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65 | #define CRGPIO_REG 0x20 /* on CPU */ |
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66 | |||
67 | void adm8668_init_clocks(void); |
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68 | |||
69 | #endif /* __ADM8668_H__ */ |