OpenWrt – Blame information for rev 2

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Rev Author Line No. Line
1 office 1 --- a/drivers/tty/serial/amba-pl010.c
2 +++ b/drivers/tty/serial/amba-pl010.c
3 @@ -48,11 +48,9 @@
4 #include <linux/slab.h>
5 #include <linux/io.h>
6  
7 -#define UART_NR 8
8 -
9 #define SERIAL_AMBA_MAJOR 204
10 #define SERIAL_AMBA_MINOR 16
11 -#define SERIAL_AMBA_NR UART_NR
12 +#define SERIAL_AMBA_NR CONFIG_SERIAL_AMBA_PL010_NUMPORTS
13  
14 #define AMBA_ISR_PASS_LIMIT 256
15  
16 @@ -78,9 +76,9 @@ static void pl010_stop_tx(struct uart_po
17 struct uart_amba_port *uap = (struct uart_amba_port *)port;
18 unsigned int cr;
19  
20 - cr = readb(uap->port.membase + UART010_CR);
21 + cr = __raw_readl(uap->port.membase + UART010_CR);
22 cr &= ~UART010_CR_TIE;
23 - writel(cr, uap->port.membase + UART010_CR);
24 + __raw_writel(cr, uap->port.membase + UART010_CR);
25 }
26  
27 static void pl010_start_tx(struct uart_port *port)
28 @@ -88,9 +86,9 @@ static void pl010_start_tx(struct uart_p
29 struct uart_amba_port *uap = (struct uart_amba_port *)port;
30 unsigned int cr;
31  
32 - cr = readb(uap->port.membase + UART010_CR);
33 + cr = __raw_readl(uap->port.membase + UART010_CR);
34 cr |= UART010_CR_TIE;
35 - writel(cr, uap->port.membase + UART010_CR);
36 + __raw_writel(cr, uap->port.membase + UART010_CR);
37 }
38  
39 static void pl010_stop_rx(struct uart_port *port)
40 @@ -98,9 +96,9 @@ static void pl010_stop_rx(struct uart_po
41 struct uart_amba_port *uap = (struct uart_amba_port *)port;
42 unsigned int cr;
43  
44 - cr = readb(uap->port.membase + UART010_CR);
45 + cr = __raw_readl(uap->port.membase + UART010_CR);
46 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
47 - writel(cr, uap->port.membase + UART010_CR);
48 + __raw_writel(cr, uap->port.membase + UART010_CR);
49 }
50  
51 static void pl010_enable_ms(struct uart_port *port)
52 @@ -108,18 +106,18 @@ static void pl010_enable_ms(struct uart_
53 struct uart_amba_port *uap = (struct uart_amba_port *)port;
54 unsigned int cr;
55  
56 - cr = readb(uap->port.membase + UART010_CR);
57 + cr = __raw_readl(uap->port.membase + UART010_CR);
58 cr |= UART010_CR_MSIE;
59 - writel(cr, uap->port.membase + UART010_CR);
60 + __raw_writel(cr, uap->port.membase + UART010_CR);
61 }
62  
63 static void pl010_rx_chars(struct uart_amba_port *uap)
64 {
65 unsigned int status, ch, flag, rsr, max_count = 256;
66  
67 - status = readb(uap->port.membase + UART01x_FR);
68 + status = __raw_readl(uap->port.membase + UART01x_FR);
69 while (UART_RX_DATA(status) && max_count--) {
70 - ch = readb(uap->port.membase + UART01x_DR);
71 + ch = __raw_readl(uap->port.membase + UART01x_DR);
72 flag = TTY_NORMAL;
73  
74 uap->port.icount.rx++;
75 @@ -128,9 +126,9 @@ static void pl010_rx_chars(struct uart_a
76 * Note that the error handling code is
77 * out of the main execution path
78 */
79 - rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
80 + rsr = __raw_readl(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
81 if (unlikely(rsr & UART01x_RSR_ANY)) {
82 - writel(0, uap->port.membase + UART01x_ECR);
83 + __raw_writel(0, uap->port.membase + UART01x_ECR);
84  
85 if (rsr & UART01x_RSR_BE) {
86 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
87 @@ -160,7 +158,7 @@ static void pl010_rx_chars(struct uart_a
88 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
89  
90 ignore_char:
91 - status = readb(uap->port.membase + UART01x_FR);
92 + status = __raw_readl(uap->port.membase + UART01x_FR);
93 }
94 spin_unlock(&uap->port.lock);
95 tty_flip_buffer_push(&uap->port.state->port);
96 @@ -173,7 +171,7 @@ static void pl010_tx_chars(struct uart_a
97 int count;
98  
99 if (uap->port.x_char) {
100 - writel(uap->port.x_char, uap->port.membase + UART01x_DR);
101 + __raw_writel(uap->port.x_char, uap->port.membase + UART01x_DR);
102 uap->port.icount.tx++;
103 uap->port.x_char = 0;
104 return;
105 @@ -185,7 +183,7 @@ static void pl010_tx_chars(struct uart_a
106  
107 count = uap->port.fifosize >> 1;
108 do {
109 - writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
110 + __raw_writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
111 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
112 uap->port.icount.tx++;
113 if (uart_circ_empty(xmit))
114 @@ -203,9 +201,9 @@ static void pl010_modem_status(struct ua
115 {
116 unsigned int status, delta;
117  
118 - writel(0, uap->port.membase + UART010_ICR);
119 + __raw_writel(0, uap->port.membase + UART010_ICR);
120  
121 - status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
122 + status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
123  
124 delta = status ^ uap->old_status;
125 uap->old_status = status;
126 @@ -233,7 +231,7 @@ static irqreturn_t pl010_int(int irq, vo
127  
128 spin_lock(&uap->port.lock);
129  
130 - status = readb(uap->port.membase + UART010_IIR);
131 + status = __raw_readl(uap->port.membase + UART010_IIR);
132 if (status) {
133 do {
134 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
135 @@ -246,7 +244,7 @@ static irqreturn_t pl010_int(int irq, vo
136 if (pass_counter-- == 0)
137 break;
138  
139 - status = readb(uap->port.membase + UART010_IIR);
140 + status = __raw_readl(uap->port.membase + UART010_IIR);
141 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
142 UART010_IIR_TIS));
143 handled = 1;
144 @@ -260,7 +258,7 @@ static irqreturn_t pl010_int(int irq, vo
145 static unsigned int pl010_tx_empty(struct uart_port *port)
146 {
147 struct uart_amba_port *uap = (struct uart_amba_port *)port;
148 - unsigned int status = readb(uap->port.membase + UART01x_FR);
149 + unsigned int status = __raw_readl(uap->port.membase + UART01x_FR);
150 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
151 }
152  
153 @@ -270,7 +268,7 @@ static unsigned int pl010_get_mctrl(stru
154 unsigned int result = 0;
155 unsigned int status;
156  
157 - status = readb(uap->port.membase + UART01x_FR);
158 + status = __raw_readl(uap->port.membase + UART01x_FR);
159 if (status & UART01x_FR_DCD)
160 result |= TIOCM_CAR;
161 if (status & UART01x_FR_DSR)
162 @@ -296,12 +294,12 @@ static void pl010_break_ctl(struct uart_
163 unsigned int lcr_h;
164  
165 spin_lock_irqsave(&uap->port.lock, flags);
166 - lcr_h = readb(uap->port.membase + UART010_LCRH);
167 + lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
168 if (break_state == -1)
169 lcr_h |= UART01x_LCRH_BRK;
170 else
171 lcr_h &= ~UART01x_LCRH_BRK;
172 - writel(lcr_h, uap->port.membase + UART010_LCRH);
173 + __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
174 spin_unlock_irqrestore(&uap->port.lock, flags);
175 }
176  
177 @@ -329,12 +327,12 @@ static int pl010_startup(struct uart_por
178 /*
179 * initialise the old status of the modem signals
180 */
181 - uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
182 + uap->old_status = __raw_readl(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
183  
184 /*
185 * Finally, enable interrupts
186 */
187 - writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
188 + __raw_writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
189 uap->port.membase + UART010_CR);
190  
191 return 0;
192 @@ -357,10 +355,10 @@ static void pl010_shutdown(struct uart_p
193 /*
194 * disable all interrupts, disable the port
195 */
196 - writel(0, uap->port.membase + UART010_CR);
197 + __raw_writel(0, uap->port.membase + UART010_CR);
198  
199 /* disable break condition and fifos */
200 - writel(readb(uap->port.membase + UART010_LCRH) &
201 + __raw_writel(__raw_readl(uap->port.membase + UART010_LCRH) &
202 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
203 uap->port.membase + UART010_LCRH);
204  
205 @@ -382,7 +380,7 @@ pl010_set_termios(struct uart_port *port
206 /*
207 * Ask the core to calculate the divisor for us.
208 */
209 - baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
210 + baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
211 quot = uart_get_divisor(port, baud);
212  
213 switch (termios->c_cflag & CSIZE) {
214 @@ -445,25 +443,25 @@ pl010_set_termios(struct uart_port *port
215 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
216  
217 /* first, disable everything */
218 - old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
219 + old_cr = __raw_readl(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
220  
221 if (UART_ENABLE_MS(port, termios->c_cflag))
222 old_cr |= UART010_CR_MSIE;
223  
224 - writel(0, uap->port.membase + UART010_CR);
225 + __raw_writel(0, uap->port.membase + UART010_CR);
226  
227 /* Set baud rate */
228 quot -= 1;
229 - writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
230 - writel(quot & 0xff, uap->port.membase + UART010_LCRL);
231 + __raw_writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
232 + __raw_writel(quot & 0xff, uap->port.membase + UART010_LCRL);
233  
234 /*
235 * ----------v----------v----------v----------v-----
236 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
237 * ----------^----------^----------^----------^-----
238 */
239 - writel(lcr_h, uap->port.membase + UART010_LCRH);
240 - writel(old_cr, uap->port.membase + UART010_CR);
241 + __raw_writel(lcr_h, uap->port.membase + UART010_LCRH);
242 + __raw_writel(old_cr, uap->port.membase + UART010_CR);
243  
244 spin_unlock_irqrestore(&uap->port.lock, flags);
245 }
246 @@ -545,7 +543,7 @@ static struct uart_ops amba_pl010_pops =
247 .verify_port = pl010_verify_port,
248 };
249  
250 -static struct uart_amba_port *amba_ports[UART_NR];
251 +static struct uart_amba_port *amba_ports[SERIAL_AMBA_NR];
252  
253 #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
254  
255 @@ -555,10 +553,10 @@ static void pl010_console_putchar(struct
256 unsigned int status;
257  
258 do {
259 - status = readb(uap->port.membase + UART01x_FR);
260 + status = __raw_readl(uap->port.membase + UART01x_FR);
261 barrier();
262 } while (!UART_TX_READY(status));
263 - writel(ch, uap->port.membase + UART01x_DR);
264 + __raw_writel(ch, uap->port.membase + UART01x_DR);
265 }
266  
267 static void
268 @@ -572,8 +570,8 @@ pl010_console_write(struct console *co,
269 /*
270 * First save the CR then disable the interrupts
271 */
272 - old_cr = readb(uap->port.membase + UART010_CR);
273 - writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
274 + old_cr = __raw_readl(uap->port.membase + UART010_CR);
275 + __raw_writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
276  
277 uart_console_write(&uap->port, s, count, pl010_console_putchar);
278  
279 @@ -582,10 +580,10 @@ pl010_console_write(struct console *co,
280 * and restore the TCR
281 */
282 do {
283 - status = readb(uap->port.membase + UART01x_FR);
284 + status = __raw_readl(uap->port.membase + UART01x_FR);
285 barrier();
286 } while (status & UART01x_FR_BUSY);
287 - writel(old_cr, uap->port.membase + UART010_CR);
288 + __raw_writel(old_cr, uap->port.membase + UART010_CR);
289  
290 clk_disable(uap->clk);
291 }
292 @@ -594,9 +592,9 @@ static void __init
293 pl010_console_get_options(struct uart_amba_port *uap, int *baud,
294 int *parity, int *bits)
295 {
296 - if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
297 + if (__raw_readl(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
298 unsigned int lcr_h, quot;
299 - lcr_h = readb(uap->port.membase + UART010_LCRH);
300 + lcr_h = __raw_readl(uap->port.membase + UART010_LCRH);
301  
302 *parity = 'n';
303 if (lcr_h & UART01x_LCRH_PEN) {
304 @@ -611,8 +609,8 @@ pl010_console_get_options(struct uart_am
305 else
306 *bits = 8;
307  
308 - quot = readb(uap->port.membase + UART010_LCRL) |
309 - readb(uap->port.membase + UART010_LCRM) << 8;
310 + quot = __raw_readl(uap->port.membase + UART010_LCRL) |
311 + __raw_readl(uap->port.membase + UART010_LCRM) << 8;
312 *baud = uap->port.uartclk / (16 * (quot + 1));
313 }
314 }
315 @@ -631,7 +629,7 @@ static int __init pl010_console_setup(st
316 * if so, search for the first available port that does have
317 * console support.
318 */
319 - if (co->index >= UART_NR)
320 + if (co->index >= SERIAL_AMBA_NR)
321 co->index = 0;
322 uap = amba_ports[co->index];
323 if (!uap)
324 @@ -673,7 +671,7 @@ static struct uart_driver amba_reg = {
325 .dev_name = "ttyAM",
326 .major = SERIAL_AMBA_MAJOR,
327 .minor = SERIAL_AMBA_MINOR,
328 - .nr = UART_NR,
329 + .nr = SERIAL_AMBA_NR,
330 .cons = AMBA_CONSOLE,
331 };
332  
333 --- a/drivers/tty/serial/Kconfig
334 +++ b/drivers/tty/serial/Kconfig
335 @@ -25,10 +25,18 @@ config SERIAL_AMBA_PL010
336 help
337 This selects the ARM(R) AMBA(R) PrimeCell PL010 UART. If you have
338 an Integrator/AP or Integrator/PP2 platform, or if you have a
339 - Cirrus Logic EP93xx CPU, say Y or M here.
340 + Cirrus Logic EP93xx CPU or an Infineon ADM5120 SOC, say Y or M here.
341  
342 If unsure, say N.
343  
344 +config SERIAL_AMBA_PL010_NUMPORTS
345 + int "Maximum number of AMBA PL010 serial ports"
346 + depends on SERIAL_AMBA_PL010
347 + default "8"
348 + ---help---
349 + Set this to the number of serial ports you want the AMBA PL010 driver
350 + to support.
351 +
352 config SERIAL_AMBA_PL010_CONSOLE
353 bool "Support for console on AMBA serial port"
354 depends on SERIAL_AMBA_PL010=y