OpenWrt – Blame information for rev 1
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| Rev | Author | Line No. | Line |
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| 1 | office | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> |
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| 7 | */ |
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| 8 | #ifndef __ASM_MIPS_MACH_ADM5120_WAR_H |
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| 9 | #define __ASM_MIPS_MACH_ADM5120_WAR_H |
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| 10 | |||
| 11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 |
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| 12 | #define R4600_V1_HIT_CACHEOP_WAR 0 |
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| 13 | #define R4600_V2_HIT_CACHEOP_WAR 0 |
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| 14 | #define R5432_CP0_INTERRUPT_WAR 0 |
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| 15 | #define BCM1250_M3_WAR 0 |
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| 16 | #define SIBYTE_1956_WAR 0 |
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| 17 | #define MIPS4K_ICACHE_REFILL_WAR 0 |
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| 18 | #define MIPS_CACHE_SYNC_WAR 0 |
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| 19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 |
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| 20 | #define RM9000_CDEX_SMP_WAR 0 |
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| 21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 |
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| 22 | #define R10000_LLSC_WAR 0 |
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| 23 | #define MIPS34K_MISSED_ITLB_WAR 0 |
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| 24 | |||
| 25 | #endif /* __ASM_MIPS_MACH_ADM5120_WAR_H */ |